1 /* 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #ifndef _LPC32XX_CPU_H 21 #define _LPC32XX_CPU_H 22 23 /* LPC32XX Memory map */ 24 25 /* AHB physical base addresses */ 26 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ 27 #define SSP0_BASE 0x20084000 /* SSP0 registers base */ 28 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ 29 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ 30 #define DMA_BASE 0x31000000 /* DMA controller registers base */ 31 #define USB_BASE 0x31020000 /* USB registers base */ 32 #define LCD_BASE 0x31040000 /* LCD registers base */ 33 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ 34 #define EMC_BASE 0x31080000 /* EMC configuration registers base */ 35 36 /* FAB peripherals base addresses */ 37 #define CLK_PM_BASE 0x40004000 /* System control registers base */ 38 #define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ 39 #define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ 40 #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ 41 #define RTC_BASE 0x40024000 /* RTC registers base */ 42 #define GPIO_BASE 0x40028000 /* GPIO registers base */ 43 #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ 44 #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ 45 #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ 46 #define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ 47 48 /* APB peripherals base addresses */ 49 #define UART3_BASE 0x40080000 /* UART 3 registers base */ 50 #define UART4_BASE 0x40088000 /* UART 4 registers base */ 51 #define UART5_BASE 0x40090000 /* UART 5 registers base */ 52 #define UART6_BASE 0x40098000 /* UART 6 registers base */ 53 54 /* External SDRAM Memory Bank base addresses */ 55 #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ 56 #define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ 57 58 /* External Static Memory Bank base addresses */ 59 #define EMC_CS0_BASE 0xE0000000 60 #define EMC_CS1_BASE 0xE1000000 61 #define EMC_CS2_BASE 0xE2000000 62 #define EMC_CS3_BASE 0xE3000000 63 64 #endif /* _LPC32XX_CPU_H */ 65