1*52f69f81SVladimir Zapolskiy /* 2*52f69f81SVladimir Zapolskiy * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*52f69f81SVladimir Zapolskiy * 4*52f69f81SVladimir Zapolskiy * This program is free software; you can redistribute it and/or 5*52f69f81SVladimir Zapolskiy * modify it under the terms of the GNU General Public License 6*52f69f81SVladimir Zapolskiy * as published by the Free Software Foundation; either version 2 7*52f69f81SVladimir Zapolskiy * of the License, or (at your option) any later version. 8*52f69f81SVladimir Zapolskiy * 9*52f69f81SVladimir Zapolskiy * This program is distributed in the hope that it will be useful, 10*52f69f81SVladimir Zapolskiy * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*52f69f81SVladimir Zapolskiy * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*52f69f81SVladimir Zapolskiy * GNU General Public License for more details. 13*52f69f81SVladimir Zapolskiy * 14*52f69f81SVladimir Zapolskiy * You should have received a copy of the GNU General Public License 15*52f69f81SVladimir Zapolskiy * along with this program; if not, write to the Free Software 16*52f69f81SVladimir Zapolskiy * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17*52f69f81SVladimir Zapolskiy * MA 02110-1301, USA. 18*52f69f81SVladimir Zapolskiy */ 19*52f69f81SVladimir Zapolskiy 20*52f69f81SVladimir Zapolskiy #ifndef _LPC32XX_CPU_H 21*52f69f81SVladimir Zapolskiy #define _LPC32XX_CPU_H 22*52f69f81SVladimir Zapolskiy 23*52f69f81SVladimir Zapolskiy /* LPC32XX Memory map */ 24*52f69f81SVladimir Zapolskiy 25*52f69f81SVladimir Zapolskiy /* AHB physical base addresses */ 26*52f69f81SVladimir Zapolskiy #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */ 27*52f69f81SVladimir Zapolskiy #define SSP0_BASE 0x20084000 /* SSP0 registers base */ 28*52f69f81SVladimir Zapolskiy #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ 29*52f69f81SVladimir Zapolskiy #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */ 30*52f69f81SVladimir Zapolskiy #define DMA_BASE 0x31000000 /* DMA controller registers base */ 31*52f69f81SVladimir Zapolskiy #define USB_BASE 0x31020000 /* USB registers base */ 32*52f69f81SVladimir Zapolskiy #define LCD_BASE 0x31040000 /* LCD registers base */ 33*52f69f81SVladimir Zapolskiy #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */ 34*52f69f81SVladimir Zapolskiy #define EMC_BASE 0x31080000 /* EMC configuration registers base */ 35*52f69f81SVladimir Zapolskiy 36*52f69f81SVladimir Zapolskiy /* FAB peripherals base addresses */ 37*52f69f81SVladimir Zapolskiy #define CLK_PM_BASE 0x40004000 /* System control registers base */ 38*52f69f81SVladimir Zapolskiy #define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */ 39*52f69f81SVladimir Zapolskiy #define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */ 40*52f69f81SVladimir Zapolskiy #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ 41*52f69f81SVladimir Zapolskiy #define RTC_BASE 0x40024000 /* RTC registers base */ 42*52f69f81SVladimir Zapolskiy #define GPIO_BASE 0x40028000 /* GPIO registers base */ 43*52f69f81SVladimir Zapolskiy #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ 44*52f69f81SVladimir Zapolskiy #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ 45*52f69f81SVladimir Zapolskiy #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ 46*52f69f81SVladimir Zapolskiy #define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */ 47*52f69f81SVladimir Zapolskiy 48*52f69f81SVladimir Zapolskiy /* APB peripherals base addresses */ 49*52f69f81SVladimir Zapolskiy #define UART3_BASE 0x40080000 /* UART 3 registers base */ 50*52f69f81SVladimir Zapolskiy #define UART4_BASE 0x40088000 /* UART 4 registers base */ 51*52f69f81SVladimir Zapolskiy #define UART5_BASE 0x40090000 /* UART 5 registers base */ 52*52f69f81SVladimir Zapolskiy #define UART6_BASE 0x40098000 /* UART 6 registers base */ 53*52f69f81SVladimir Zapolskiy 54*52f69f81SVladimir Zapolskiy /* External SDRAM Memory Bank base addresses */ 55*52f69f81SVladimir Zapolskiy #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ 56*52f69f81SVladimir Zapolskiy #define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */ 57*52f69f81SVladimir Zapolskiy 58*52f69f81SVladimir Zapolskiy /* External Static Memory Bank base addresses */ 59*52f69f81SVladimir Zapolskiy #define EMC_CS0_BASE 0xE0000000 60*52f69f81SVladimir Zapolskiy #define EMC_CS1_BASE 0xE1000000 61*52f69f81SVladimir Zapolskiy #define EMC_CS2_BASE 0xE2000000 62*52f69f81SVladimir Zapolskiy #define EMC_CS3_BASE 0xE3000000 63*52f69f81SVladimir Zapolskiy 64*52f69f81SVladimir Zapolskiy #endif /* _LPC32XX_CPU_H */ 65