1 /* 2 * Common definitions for LPC32XX board configurations 3 * 4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _LPC32XX_CONFIG_H 10 #define _LPC32XX_CONFIG_H 11 12 13 /* Basic CPU architecture */ 14 #define CONFIG_ARCH_CPU_INIT 15 16 #define CONFIG_NR_DRAM_BANKS_MAX 2 17 18 /* UART configuration */ 19 #if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) 20 #define CONFIG_SYS_NS16550_SERIAL 21 #define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) 22 #elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ 23 (CONFIG_SYS_LPC32XX_UART == 7) 24 #define CONFIG_LPC32XX_HSUART 25 #else 26 #error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" 27 #endif 28 29 #if defined(CONFIG_SYS_NS16550_SERIAL) 30 #define CONFIG_SYS_NS16550 31 32 #define CONFIG_SYS_NS16550_REG_SIZE -4 33 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 34 35 #define CONFIG_SYS_NS16550_COM1 UART3_BASE 36 #define CONFIG_SYS_NS16550_COM2 UART4_BASE 37 #define CONFIG_SYS_NS16550_COM3 UART5_BASE 38 #define CONFIG_SYS_NS16550_COM4 UART6_BASE 39 #endif 40 41 #if defined(CONFIG_LPC32XX_HSUART) 42 #if CONFIG_SYS_LPC32XX_UART == 1 43 #define HS_UART_BASE HS_UART1_BASE 44 #elif CONFIG_SYS_LPC32XX_UART == 2 45 #define HS_UART_BASE HS_UART2_BASE 46 #else /* CONFIG_SYS_LPC32XX_UART == 7 */ 47 #define HS_UART_BASE HS_UART7_BASE 48 #endif 49 #endif 50 51 #define CONFIG_SYS_BAUDRATE_TABLE \ 52 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } 53 54 /* Ethernet */ 55 #define LPC32XX_ETH_BASE ETHERNET_BASE 56 57 /* NAND */ 58 #if defined(CONFIG_NAND_LPC32XX_SLC) 59 #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 60 #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 61 62 #if !defined(CONFIG_SYS_NAND_PAGE_SIZE) 63 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 64 #endif 65 66 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) 67 #define CONFIG_SYS_NAND_OOBSIZE 64 68 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 69 48, 49, 50, 51, 52, 53, 54, 55, \ 70 56, 57, 58, 59, 60, 61, 62, 63, } 71 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 72 #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) 73 #define CONFIG_SYS_NAND_OOBSIZE 16 74 #define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } 75 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 76 #else 77 #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" 78 #endif 79 80 #define CONFIG_SYS_NAND_ECCSIZE 0x100 81 #define CONFIG_SYS_NAND_ECCBYTES 3 82 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 83 CONFIG_SYS_NAND_PAGE_SIZE) 84 #endif /* CONFIG_NAND_LPC32XX_SLC */ 85 86 /* NOR Flash */ 87 #if defined(CONFIG_SYS_FLASH_CFI) 88 #define CONFIG_FLASH_CFI_DRIVER 89 #define CONFIG_SYS_FLASH_PROTECTION 90 #endif 91 92 /* USB OHCI */ 93 #if defined(CONFIG_USB_OHCI_LPC32XX) 94 #define CONFIG_USB_OHCI_NEW 95 #define CONFIG_SYS_USB_OHCI_CPU_INIT 96 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 97 #define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE 98 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" 99 #endif 100 101 #endif /* _LPC32XX_CONFIG_H */ 102