1 /* 2 * Common definitions for LPC32XX board configurations 3 * 4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _LPC32XX_CONFIG_H 10 #define _LPC32XX_CONFIG_H 11 12 #define CONFIG_SYS_GENERIC_BOARD 13 14 /* Basic CPU architecture */ 15 #define CONFIG_ARCH_CPU_INIT 16 17 #define CONFIG_NR_DRAM_BANKS_MAX 2 18 19 /* UART configuration */ 20 #if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) 21 #define CONFIG_SYS_NS16550_SERIAL 22 #define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) 23 #elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ 24 (CONFIG_SYS_LPC32XX_UART == 7) 25 #define CONFIG_LPC32XX_HSUART 26 #else 27 #error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" 28 #endif 29 30 #if defined(CONFIG_SYS_NS16550_SERIAL) 31 #define CONFIG_SYS_NS16550 32 33 #define CONFIG_SYS_NS16550_REG_SIZE -4 34 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 35 36 #define CONFIG_SYS_NS16550_COM1 UART3_BASE 37 #define CONFIG_SYS_NS16550_COM2 UART4_BASE 38 #define CONFIG_SYS_NS16550_COM3 UART5_BASE 39 #define CONFIG_SYS_NS16550_COM4 UART6_BASE 40 #endif 41 42 #if defined(CONFIG_LPC32XX_HSUART) 43 #if CONFIG_SYS_LPC32XX_UART == 1 44 #define HS_UART_BASE HS_UART1_BASE 45 #elif CONFIG_SYS_LPC32XX_UART == 2 46 #define HS_UART_BASE HS_UART2_BASE 47 #else /* CONFIG_SYS_LPC32XX_UART == 7 */ 48 #define HS_UART_BASE HS_UART7_BASE 49 #endif 50 #endif 51 52 #define CONFIG_SYS_BAUDRATE_TABLE \ 53 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } 54 55 /* Ethernet */ 56 #define LPC32XX_ETH_BASE ETHERNET_BASE 57 58 /* NAND */ 59 #if defined(CONFIG_NAND_LPC32XX_SLC) 60 #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 61 #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 62 63 #if !defined(CONFIG_SYS_NAND_PAGE_SIZE) 64 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 65 #endif 66 67 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) 68 #define CONFIG_SYS_NAND_OOBSIZE 64 69 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 70 48, 49, 50, 51, 52, 53, 54, 55, \ 71 56, 57, 58, 59, 60, 61, 62, 63, } 72 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 73 #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) 74 #define CONFIG_SYS_NAND_OOBSIZE 16 75 #define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } 76 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 77 #else 78 #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" 79 #endif 80 81 #define CONFIG_SYS_NAND_ECCSIZE 0x100 82 #define CONFIG_SYS_NAND_ECCBYTES 3 83 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 84 CONFIG_SYS_NAND_PAGE_SIZE) 85 #endif /* CONFIG_NAND_LPC32XX_SLC */ 86 87 /* NOR Flash */ 88 #if defined(CONFIG_SYS_FLASH_CFI) 89 #define CONFIG_FLASH_CFI_DRIVER 90 #define CONFIG_SYS_FLASH_PROTECTION 91 #endif 92 93 /* USB OHCI */ 94 #if defined(CONFIG_USB_OHCI_LPC32XX) 95 #define CONFIG_USB_OHCI_NEW 96 #define CONFIG_SYS_USB_OHCI_CPU_INIT 97 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 98 #define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE 99 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" 100 #endif 101 102 #endif /* _LPC32XX_CONFIG_H */ 103