1 /* 2 * Common definitions for LPC32XX board configurations 3 * 4 * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _LPC32XX_CONFIG_H 10 #define _LPC32XX_CONFIG_H 11 12 /* Basic CPU architecture */ 13 #define CONFIG_ARM926EJS 14 #define CONFIG_ARCH_CPU_INIT 15 16 #define CONFIG_NR_DRAM_BANKS_MAX 2 17 18 /* UART configuration */ 19 #if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) 20 #define CONFIG_SYS_NS16550_SERIAL 21 #define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) 22 #elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ 23 (CONFIG_SYS_LPC32XX_UART == 7) 24 #define CONFIG_LPC32XX_HSUART 25 #else 26 #error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" 27 #endif 28 29 #if defined(CONFIG_SYS_NS16550_SERIAL) 30 #define CONFIG_SYS_NS16550 31 32 #define CONFIG_SYS_NS16550_REG_SIZE -4 33 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 34 35 #define CONFIG_SYS_NS16550_COM1 UART3_BASE 36 #define CONFIG_SYS_NS16550_COM2 UART4_BASE 37 #define CONFIG_SYS_NS16550_COM3 UART5_BASE 38 #define CONFIG_SYS_NS16550_COM4 UART6_BASE 39 #endif 40 41 #if defined(CONFIG_LPC32XX_HSUART) 42 #if CONFIG_SYS_LPC32XX_UART == 1 43 #define HS_UART_BASE HS_UART1_BASE 44 #elif CONFIG_SYS_LPC32XX_UART == 2 45 #define HS_UART_BASE HS_UART2_BASE 46 #else /* CONFIG_SYS_LPC32XX_UART == 7 */ 47 #define HS_UART_BASE HS_UART7_BASE 48 #endif 49 #endif 50 51 #define CONFIG_SYS_BAUDRATE_TABLE \ 52 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } 53 54 /* NOR Flash */ 55 #if defined(CONFIG_SYS_FLASH_CFI) 56 #define CONFIG_FLASH_CFI_DRIVER 57 #define CONFIG_SYS_FLASH_PROTECTION 58 #endif 59 60 #endif /* _LPC32XX_CONFIG_H */ 61