1 /* 2 * Common definitions for LPC32XX board configurations 3 * 4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _LPC32XX_CONFIG_H 10 #define _LPC32XX_CONFIG_H 11 12 13 /* Basic CPU architecture */ 14 #define CONFIG_ARCH_CPU_INIT 15 16 #define CONFIG_NR_DRAM_BANKS_MAX 2 17 18 /* UART configuration */ 19 #if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) 20 #define CONFIG_SYS_NS16550_SERIAL 21 #define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) 22 #elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \ 23 (CONFIG_SYS_LPC32XX_UART == 7) 24 #define CONFIG_LPC32XX_HSUART 25 #else 26 #error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" 27 #endif 28 29 #if defined(CONFIG_SYS_NS16550_SERIAL) 30 31 #define CONFIG_SYS_NS16550_REG_SIZE -4 32 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 33 34 #define CONFIG_SYS_NS16550_COM1 UART3_BASE 35 #define CONFIG_SYS_NS16550_COM2 UART4_BASE 36 #define CONFIG_SYS_NS16550_COM3 UART5_BASE 37 #define CONFIG_SYS_NS16550_COM4 UART6_BASE 38 #endif 39 40 #if defined(CONFIG_LPC32XX_HSUART) 41 #if CONFIG_SYS_LPC32XX_UART == 1 42 #define HS_UART_BASE HS_UART1_BASE 43 #elif CONFIG_SYS_LPC32XX_UART == 2 44 #define HS_UART_BASE HS_UART2_BASE 45 #else /* CONFIG_SYS_LPC32XX_UART == 7 */ 46 #define HS_UART_BASE HS_UART7_BASE 47 #endif 48 #endif 49 50 #define CONFIG_SYS_BAUDRATE_TABLE \ 51 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } 52 53 /* Ethernet */ 54 #define LPC32XX_ETH_BASE ETHERNET_BASE 55 56 /* NAND */ 57 #if defined(CONFIG_NAND_LPC32XX_SLC) 58 #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 59 #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 60 61 #if !defined(CONFIG_SYS_NAND_PAGE_SIZE) 62 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 63 #endif 64 65 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) 66 #define CONFIG_SYS_NAND_OOBSIZE 64 67 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 68 48, 49, 50, 51, 52, 53, 54, 55, \ 69 56, 57, 58, 59, 60, 61, 62, 63, } 70 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 71 #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) 72 #define CONFIG_SYS_NAND_OOBSIZE 16 73 #define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } 74 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 75 #else 76 #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" 77 #endif 78 79 #define CONFIG_SYS_NAND_ECCSIZE 0x100 80 #define CONFIG_SYS_NAND_ECCBYTES 3 81 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 82 CONFIG_SYS_NAND_PAGE_SIZE) 83 #endif /* CONFIG_NAND_LPC32XX_SLC */ 84 85 /* NOR Flash */ 86 #if defined(CONFIG_SYS_FLASH_CFI) 87 #define CONFIG_FLASH_CFI_DRIVER 88 #define CONFIG_SYS_FLASH_PROTECTION 89 #endif 90 91 /* USB OHCI */ 92 #if defined(CONFIG_USB_OHCI_LPC32XX) 93 #define CONFIG_USB_OHCI_NEW 94 #define CONFIG_SYS_USB_OHCI_CPU_INIT 95 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 96 #define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE 97 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci" 98 #endif 99 100 #endif /* _LPC32XX_CONFIG_H */ 101