1 /* 2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #ifndef _LPC32XX_CLK_H 21 #define _LPC32XX_CLK_H 22 23 #include <asm/types.h> 24 25 #define OSC_CLK_FREQUENCY 13000000 26 #define RTC_CLK_FREQUENCY 32768 27 28 /* Clocking and Power Control Registers */ 29 struct clk_pm_regs { 30 u32 reserved0[5]; 31 u32 boot_map; /* Boot Map Control Register */ 32 u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */ 33 u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */ 34 /* Internal Start Signal Sources Registers */ 35 u32 start_er_int; /* Start Enable Register */ 36 u32 start_rsr_int; /* Start Raw Status Register */ 37 u32 start_sr_int; /* Start Status Register */ 38 u32 start_apr_int; /* Start Activation Polarity Register */ 39 /* Device Pin Start Signal Sources Registers */ 40 u32 start_er_pin; /* Start Enable Register */ 41 u32 start_rsr_pin; /* Start Raw Status Register */ 42 u32 start_sr_pin; /* Start Status Register */ 43 u32 start_apr_pin; /* Start Activation Polarity Register */ 44 /* Clock Control Registers */ 45 u32 hclkdiv_ctrl; /* HCLK Divider Control Register */ 46 u32 pwr_ctrl; /* Power Control Register */ 47 u32 pll397_ctrl; /* PLL397 Control Register */ 48 u32 osc_ctrl; /* Main Oscillator Control Register */ 49 u32 sysclk_ctrl; /* SYSCLK Control Register */ 50 u32 lcdclk_ctrl; /* LCD Clock Control Register */ 51 u32 hclkpll_ctrl; /* HCLK PLL Control Register */ 52 u32 reserved1; 53 u32 adclk_ctrl1; /* ADC Clock Control1 Register */ 54 u32 usb_ctrl; /* USB Control Register */ 55 u32 sdramclk_ctrl; /* SDRAM Clock Control Register */ 56 u32 ddr_lap_nom; /* DDR Calibration Nominal Value */ 57 u32 ddr_lap_count; /* DDR Calibration Measured Value */ 58 u32 ddr_cal_delay; /* DDR Calibration Delay Value */ 59 u32 ssp_ctrl; /* SSP Control Register */ 60 u32 i2s_ctrl; /* I2S Clock Control Register */ 61 u32 ms_ctrl; /* Memory Card Control Register */ 62 u32 reserved2[3]; 63 u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */ 64 u32 reserved3[4]; 65 u32 test_clk; /* Test Clock Selection Register */ 66 u32 sw_int; /* Software Interrupt Register */ 67 u32 i2cclk_ctrl; /* I2C Clock Control Register */ 68 u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */ 69 u32 adclk_ctrl; /* ADC Clock Control Register */ 70 u32 pwmclk_ctrl; /* PWM Clock Control Register */ 71 u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */ 72 u32 timclk_ctrl1; /* Motor and Timer Clock Control */ 73 u32 spi_ctrl; /* SPI Control Register */ 74 u32 flashclk_ctrl; /* NAND Flash Clock Control Register */ 75 u32 reserved4; 76 u32 u3clk; /* UART 3 Clock Control Register */ 77 u32 u4clk; /* UART 4 Clock Control Register */ 78 u32 u5clk; /* UART 5 Clock Control Register */ 79 u32 u6clk; /* UART 6 Clock Control Register */ 80 u32 irdaclk; /* IrDA Clock Control Register */ 81 u32 uartclk_ctrl; /* UART Clock Control Register */ 82 u32 dmaclk_ctrl; /* DMA Clock Control Register */ 83 u32 autoclk_ctrl; /* Autoclock Control Register */ 84 }; 85 86 /* HCLK Divider Control Register bits */ 87 #define CLK_HCLK_DDRAM_HALF (0x2 << 7) 88 #define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) 89 #define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) 90 #define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2) 91 #define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2) 92 #define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0) 93 #define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) 94 #define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) 95 #define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) 96 97 /* Power Control Register bits */ 98 #define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) 99 #define CLK_PWR_EMC_SREFREQ (1 << 9) 100 #define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) 101 #define CLK_PWR_SDRAM_SREFREQ (1 << 7) 102 #define CLK_PWR_HIGHCORE_LEVEL (1 << 5) 103 #define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) 104 #define CLK_PWR_SYSCLKEN_CTRL (1 << 3) 105 #define CLK_PWR_NORMAL_RUN (1 << 2) 106 #define CLK_PWR_HIGHCORE_CTRL (1 << 1) 107 #define CLK_PWR_STOP_MODE (1 << 0) 108 109 /* SYSCLK Control Register bits */ 110 #define CLK_SYSCLK_PLL397 (1 << 1) 111 #define CLK_SYSCLK_MUX (1 << 0) 112 113 /* HCLK PLL Control Register bits */ 114 #define CLK_HCLK_PLL_OPERATING (1 << 16) 115 #define CLK_HCLK_PLL_BYPASS (1 << 15) 116 #define CLK_HCLK_PLL_DIRECT (1 << 14) 117 #define CLK_HCLK_PLL_FEEDBACK (1 << 13) 118 #define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) 119 #define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) 120 #define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) 121 #define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11) 122 #define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11) 123 #define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9) 124 #define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9) 125 #define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9) 126 #define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9) 127 #define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) 128 #define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) 129 #define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) 130 #define CLK_HCLK_PLL_LOCKED (1 << 0) 131 132 /* Ethernet MAC Clock Control Register bits */ 133 #define CLK_MAC_RMII (0x3 << 3) 134 #define CLK_MAC_MII (0x1 << 3) 135 #define CLK_MAC_MASTER (1 << 2) 136 #define CLK_MAC_SLAVE (1 << 1) 137 #define CLK_MAC_REG (1 << 0) 138 139 /* Timer Clock Control1 Register bits */ 140 #define CLK_TIMCLK_MOTOR (1 << 6) 141 #define CLK_TIMCLK_TIMER3 (1 << 5) 142 #define CLK_TIMCLK_TIMER2 (1 << 4) 143 #define CLK_TIMCLK_TIMER1 (1 << 3) 144 #define CLK_TIMCLK_TIMER0 (1 << 2) 145 #define CLK_TIMCLK_TIMER5 (1 << 1) 146 #define CLK_TIMCLK_TIMER4 (1 << 0) 147 148 /* Timer Clock Control Register bits */ 149 #define CLK_TIMCLK_HSTIMER (1 << 1) 150 #define CLK_TIMCLK_WATCHDOG (1 << 0) 151 152 /* UART Clock Control Register bits */ 153 #define CLK_UART(n) (1 << ((n) - 3)) 154 155 /* UARTn Clock Select Registers bits */ 156 #define CLK_UART_HCLK (1 << 16) 157 #define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) 158 #define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0) 159 160 /* DMA Clock Control Register bits */ 161 #define CLK_DMA_ENABLE (1 << 0) 162 163 unsigned int get_sys_clk_rate(void); 164 unsigned int get_hclk_pll_rate(void); 165 unsigned int get_hclk_clk_div(void); 166 unsigned int get_hclk_clk_rate(void); 167 unsigned int get_periph_clk_div(void); 168 unsigned int get_periph_clk_rate(void); 169 170 #endif /* _LPC32XX_CLK_H */ 171