1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 */ 7 8 #ifndef _ASM_ARCH_IMX8M_CLOCK_H 9 #define _ASM_ARCH_IMX8M_CLOCK_H 10 11 #include <linux/bitops.h> 12 13 #define MHZ(X) ((X) * 1000000UL) 14 15 enum pll_clocks { 16 ANATOP_ARM_PLL, 17 ANATOP_GPU_PLL, 18 ANATOP_SYSTEM_PLL1, 19 ANATOP_SYSTEM_PLL2, 20 ANATOP_SYSTEM_PLL3, 21 ANATOP_AUDIO_PLL1, 22 ANATOP_AUDIO_PLL2, 23 ANATOP_VIDEO_PLL1, 24 ANATOP_VIDEO_PLL2, 25 ANATOP_DRAM_PLL, 26 }; 27 28 enum clk_slice_type { 29 CORE_CLOCK_SLICE, 30 BUS_CLOCK_SLICE, 31 IP_CLOCK_SLICE, 32 AHB_CLOCK_SLICE, 33 IPG_CLOCK_SLICE, 34 CORE_SEL_CLOCK_SLICE, 35 DRAM_SEL_CLOCK_SLICE, 36 }; 37 38 enum clk_root_index { 39 MXC_ARM_CLK = 0, 40 ARM_A53_CLK_ROOT = 0, 41 ARM_M4_CLK_ROOT = 1, 42 VPU_A53_CLK_ROOT = 2, 43 GPU_CORE_CLK_ROOT = 3, 44 GPU_SHADER_CLK_ROOT = 4, 45 MAIN_AXI_CLK_ROOT = 16, 46 ENET_AXI_CLK_ROOT = 17, 47 NAND_USDHC_BUS_CLK_ROOT = 18, 48 VPU_BUS_CLK_ROOT = 19, 49 DISPLAY_AXI_CLK_ROOT = 20, 50 DISPLAY_APB_CLK_ROOT = 21, 51 DISPLAY_RTRM_CLK_ROOT = 22, 52 USB_BUS_CLK_ROOT = 23, 53 GPU_AXI_CLK_ROOT = 24, 54 GPU_AHB_CLK_ROOT = 25, 55 NOC_CLK_ROOT = 26, 56 NOC_APB_CLK_ROOT = 27, 57 AHB_CLK_ROOT = 32, 58 IPG_CLK_ROOT = 33, 59 MXC_IPG_CLK = 33, 60 AUDIO_AHB_CLK_ROOT = 34, 61 MIPI_DSI_ESC_RX_CLK_ROOT = 36, 62 DRAM_SEL_CFG = 48, 63 CORE_SEL_CFG = 49, 64 DRAM_ALT_CLK_ROOT = 64, 65 DRAM_APB_CLK_ROOT = 65, 66 VPU_G1_CLK_ROOT = 66, 67 VPU_G2_CLK_ROOT = 67, 68 DISPLAY_DTRC_CLK_ROOT = 68, 69 DISPLAY_DC8000_CLK_ROOT = 69, 70 PCIE1_CTRL_CLK_ROOT = 70, 71 PCIE1_PHY_CLK_ROOT = 71, 72 PCIE1_AUX_CLK_ROOT = 72, 73 DC_PIXEL_CLK_ROOT = 73, 74 LCDIF_PIXEL_CLK_ROOT = 74, 75 SAI1_CLK_ROOT = 75, 76 SAI2_CLK_ROOT = 76, 77 SAI3_CLK_ROOT = 77, 78 SAI4_CLK_ROOT = 78, 79 SAI5_CLK_ROOT = 79, 80 SAI6_CLK_ROOT = 80, 81 SPDIF1_CLK_ROOT = 81, 82 SPDIF2_CLK_ROOT = 82, 83 ENET_REF_CLK_ROOT = 83, 84 ENET_TIMER_CLK_ROOT = 84, 85 ENET_PHY_REF_CLK_ROOT = 85, 86 NAND_CLK_ROOT = 86, 87 QSPI_CLK_ROOT = 87, 88 MXC_ESDHC_CLK = 88, 89 USDHC1_CLK_ROOT = 88, 90 MXC_ESDHC2_CLK = 89, 91 USDHC2_CLK_ROOT = 89, 92 I2C1_CLK_ROOT = 90, 93 MXC_I2C_CLK = 90, 94 I2C2_CLK_ROOT = 91, 95 I2C3_CLK_ROOT = 92, 96 I2C4_CLK_ROOT = 93, 97 UART1_CLK_ROOT = 94, 98 UART2_CLK_ROOT = 95, 99 UART3_CLK_ROOT = 96, 100 UART4_CLK_ROOT = 97, 101 USB_CORE_REF_CLK_ROOT = 98, 102 USB_PHY_REF_CLK_ROOT = 99, 103 GIC_CLK_ROOT = 100, 104 ECSPI1_CLK_ROOT = 101, 105 ECSPI2_CLK_ROOT = 102, 106 PWM1_CLK_ROOT = 103, 107 PWM2_CLK_ROOT = 104, 108 PWM3_CLK_ROOT = 105, 109 PWM4_CLK_ROOT = 106, 110 GPT1_CLK_ROOT = 107, 111 GPT2_CLK_ROOT = 108, 112 GPT3_CLK_ROOT = 109, 113 GPT4_CLK_ROOT = 110, 114 GPT5_CLK_ROOT = 111, 115 GPT6_CLK_ROOT = 112, 116 TRACE_CLK_ROOT = 113, 117 WDOG_CLK_ROOT = 114, 118 WRCLK_CLK_ROOT = 115, 119 IPP_DO_CLKO1 = 116, 120 IPP_DO_CLKO2 = 117, 121 MIPI_DSI_CORE_CLK_ROOT = 118, 122 MIPI_DSI_PHY_REF_CLK_ROOT = 119, 123 MIPI_DSI_DBI_CLK_ROOT = 120, 124 OLD_MIPI_DSI_ESC_CLK_ROOT = 121, 125 MIPI_CSI1_CORE_CLK_ROOT = 122, 126 MIPI_CSI1_PHY_REF_CLK_ROOT = 123, 127 MIPI_CSI1_ESC_CLK_ROOT = 124, 128 MIPI_CSI2_CORE_CLK_ROOT = 125, 129 MIPI_CSI2_PHY_REF_CLK_ROOT = 126, 130 MIPI_CSI2_ESC_CLK_ROOT = 127, 131 PCIE2_CTRL_CLK_ROOT = 128, 132 PCIE2_PHY_CLK_ROOT = 129, 133 PCIE2_AUX_CLK_ROOT = 130, 134 ECSPI3_CLK_ROOT = 131, 135 OLD_MIPI_DSI_ESC_RX_ROOT = 132, 136 DISPLAY_HDMI_CLK_ROOT = 133, 137 CLK_ROOT_MAX, 138 }; 139 140 enum clk_root_src { 141 OSC_25M_CLK, 142 ARM_PLL_CLK, 143 DRAM_PLL1_CLK, 144 VIDEO_PLL2_CLK, 145 VPU_PLL_CLK, 146 GPU_PLL_CLK, 147 SYSTEM_PLL1_800M_CLK, 148 SYSTEM_PLL1_400M_CLK, 149 SYSTEM_PLL1_266M_CLK, 150 SYSTEM_PLL1_200M_CLK, 151 SYSTEM_PLL1_160M_CLK, 152 SYSTEM_PLL1_133M_CLK, 153 SYSTEM_PLL1_100M_CLK, 154 SYSTEM_PLL1_80M_CLK, 155 SYSTEM_PLL1_40M_CLK, 156 SYSTEM_PLL2_1000M_CLK, 157 SYSTEM_PLL2_500M_CLK, 158 SYSTEM_PLL2_333M_CLK, 159 SYSTEM_PLL2_250M_CLK, 160 SYSTEM_PLL2_200M_CLK, 161 SYSTEM_PLL2_166M_CLK, 162 SYSTEM_PLL2_125M_CLK, 163 SYSTEM_PLL2_100M_CLK, 164 SYSTEM_PLL2_50M_CLK, 165 SYSTEM_PLL3_CLK, 166 AUDIO_PLL1_CLK, 167 AUDIO_PLL2_CLK, 168 VIDEO_PLL_CLK, 169 OSC_32K_CLK, 170 EXT_CLK_1, 171 EXT_CLK_2, 172 EXT_CLK_3, 173 EXT_CLK_4, 174 OSC_27M_CLK, 175 }; 176 177 /* CCGR index */ 178 enum clk_ccgr_index { 179 CCGR_DVFS = 0, 180 CCGR_ANAMIX = 1, 181 CCGR_CPU = 2, 182 CCGR_CSU = 4, 183 CCGR_DRAM1 = 5, 184 CCGR_DRAM2_OBSOLETE = 6, 185 CCGR_ECSPI1 = 7, 186 CCGR_ECSPI2 = 8, 187 CCGR_ECSPI3 = 9, 188 CCGR_ENET1 = 10, 189 CCGR_GPIO1 = 11, 190 CCGR_GPIO2 = 12, 191 CCGR_GPIO3 = 13, 192 CCGR_GPIO4 = 14, 193 CCGR_GPIO5 = 15, 194 CCGR_GPT1 = 16, 195 CCGR_GPT2 = 17, 196 CCGR_GPT3 = 18, 197 CCGR_GPT4 = 19, 198 CCGR_GPT5 = 20, 199 CCGR_GPT6 = 21, 200 CCGR_HS = 22, 201 CCGR_I2C1 = 23, 202 CCGR_I2C2 = 24, 203 CCGR_I2C3 = 25, 204 CCGR_I2C4 = 26, 205 CCGR_IOMUX = 27, 206 CCGR_IOMUX1 = 28, 207 CCGR_IOMUX2 = 29, 208 CCGR_IOMUX3 = 30, 209 CCGR_IOMUX4 = 31, 210 CCGR_M4 = 32, 211 CCGR_MU = 33, 212 CCGR_OCOTP = 34, 213 CCGR_OCRAM = 35, 214 CCGR_OCRAM_S = 36, 215 CCGR_PCIE = 37, 216 CCGR_PERFMON1 = 38, 217 CCGR_PERFMON2 = 39, 218 CCGR_PWM1 = 40, 219 CCGR_PWM2 = 41, 220 CCGR_PWM3 = 42, 221 CCGR_PWM4 = 43, 222 CCGR_QOS = 44, 223 CCGR_DISMIX = 45, 224 CCGR_MEGAMIX = 46, 225 CCGR_QSPI = 47, 226 CCGR_RAWNAND = 48, 227 CCGR_RDC = 49, 228 CCGR_ROM = 50, 229 CCGR_SAI1 = 51, 230 CCGR_SAI2 = 52, 231 CCGR_SAI3 = 53, 232 CCGR_SAI4 = 54, 233 CCGR_SAI5 = 55, 234 CCGR_SAI6 = 56, 235 CCGR_SCTR = 57, 236 CCGR_SDMA1 = 58, 237 CCGR_SDMA2 = 59, 238 CCGR_SEC_DEBUG = 60, 239 CCGR_SEMA1 = 61, 240 CCGR_SEMA2 = 62, 241 CCGR_SIM_DISPLAY = 63, 242 CCGR_SIM_ENET = 64, 243 CCGR_SIM_M = 65, 244 CCGR_SIM_MAIN = 66, 245 CCGR_SIM_S = 67, 246 CCGR_SIM_WAKEUP = 68, 247 CCGR_SIM_USB = 69, 248 CCGR_SIM_VPU = 70, 249 CCGR_SNVS = 71, 250 CCGR_TRACE = 72, 251 CCGR_UART1 = 73, 252 CCGR_UART2 = 74, 253 CCGR_UART3 = 75, 254 CCGR_UART4 = 76, 255 CCGR_USB_CTRL1 = 77, 256 CCGR_USB_CTRL2 = 78, 257 CCGR_USB_PHY1 = 79, 258 CCGR_USB_PHY2 = 80, 259 CCGR_USDHC1 = 81, 260 CCGR_USDHC2 = 82, 261 CCGR_WDOG1 = 83, 262 CCGR_WDOG2 = 84, 263 CCGR_WDOG3 = 85, 264 CCGR_VA53 = 86, 265 CCGR_GPU = 87, 266 CCGR_HEVC = 88, 267 CCGR_AVC = 89, 268 CCGR_VP9 = 90, 269 CCGR_HEVC_INTER = 91, 270 CCGR_GIC = 92, 271 CCGR_DISPLAY = 93, 272 CCGR_HDMI = 94, 273 CCGR_HDMI_PHY = 95, 274 CCGR_XTAL = 96, 275 CCGR_PLL = 97, 276 CCGR_TSENSOR = 98, 277 CCGR_VPU_DEC = 99, 278 CCGR_PCIE2 = 100, 279 CCGR_MIPI_CSI1 = 101, 280 CCGR_MIPI_CSI2 = 102, 281 CCGR_MAX, 282 }; 283 284 /* src index */ 285 enum clk_src_index { 286 CLK_SRC_CKIL_SYNC_REQ = 0, 287 CLK_SRC_ARM_PLL_EN = 1, 288 CLK_SRC_GPU_PLL_EN = 2, 289 CLK_SRC_VPU_PLL_EN = 3, 290 CLK_SRC_DRAM_PLL_EN = 4, 291 CLK_SRC_SYSTEM_PLL1_EN = 5, 292 CLK_SRC_SYSTEM_PLL2_EN = 6, 293 CLK_SRC_SYSTEM_PLL3_EN = 7, 294 CLK_SRC_AUDIO_PLL1_EN = 8, 295 CLK_SRC_AUDIO_PLL2_EN = 9, 296 CLK_SRC_VIDEO_PLL1_EN = 10, 297 CLK_SRC_VIDEO_PLL2_EN = 11, 298 CLK_SRC_ARM_PLL = 12, 299 CLK_SRC_GPU_PLL = 13, 300 CLK_SRC_VPU_PLL = 14, 301 CLK_SRC_DRAM_PLL = 15, 302 CLK_SRC_SYSTEM_PLL1_800M = 16, 303 CLK_SRC_SYSTEM_PLL1_400M = 17, 304 CLK_SRC_SYSTEM_PLL1_266M = 18, 305 CLK_SRC_SYSTEM_PLL1_200M = 19, 306 CLK_SRC_SYSTEM_PLL1_160M = 20, 307 CLK_SRC_SYSTEM_PLL1_133M = 21, 308 CLK_SRC_SYSTEM_PLL1_100M = 22, 309 CLK_SRC_SYSTEM_PLL1_80M = 23, 310 CLK_SRC_SYSTEM_PLL1_40M = 24, 311 CLK_SRC_SYSTEM_PLL2_1000M = 25, 312 CLK_SRC_SYSTEM_PLL2_500M = 26, 313 CLK_SRC_SYSTEM_PLL2_333M = 27, 314 CLK_SRC_SYSTEM_PLL2_250M = 28, 315 CLK_SRC_SYSTEM_PLL2_200M = 29, 316 CLK_SRC_SYSTEM_PLL2_166M = 30, 317 CLK_SRC_SYSTEM_PLL2_125M = 31, 318 CLK_SRC_SYSTEM_PLL2_100M = 32, 319 CLK_SRC_SYSTEM_PLL2_50M = 33, 320 CLK_SRC_SYSTEM_PLL3 = 34, 321 CLK_SRC_AUDIO_PLL1 = 35, 322 CLK_SRC_AUDIO_PLL2 = 36, 323 CLK_SRC_VIDEO_PLL1 = 37, 324 CLK_SRC_VIDEO_PLL2 = 38, 325 CLK_SRC_OSC_25M = 39, 326 CLK_SRC_OSC_27M = 40, 327 }; 328 329 enum root_pre_div { 330 CLK_ROOT_PRE_DIV1 = 0, 331 CLK_ROOT_PRE_DIV2, 332 CLK_ROOT_PRE_DIV3, 333 CLK_ROOT_PRE_DIV4, 334 CLK_ROOT_PRE_DIV5, 335 CLK_ROOT_PRE_DIV6, 336 CLK_ROOT_PRE_DIV7, 337 CLK_ROOT_PRE_DIV8, 338 }; 339 340 enum root_post_div { 341 CLK_ROOT_POST_DIV1 = 0, 342 CLK_ROOT_POST_DIV2, 343 CLK_ROOT_POST_DIV3, 344 CLK_ROOT_POST_DIV4, 345 CLK_ROOT_POST_DIV5, 346 CLK_ROOT_POST_DIV6, 347 CLK_ROOT_POST_DIV7, 348 CLK_ROOT_POST_DIV8, 349 CLK_ROOT_POST_DIV9, 350 CLK_ROOT_POST_DIV10, 351 CLK_ROOT_POST_DIV11, 352 CLK_ROOT_POST_DIV12, 353 CLK_ROOT_POST_DIV13, 354 CLK_ROOT_POST_DIV14, 355 CLK_ROOT_POST_DIV15, 356 CLK_ROOT_POST_DIV16, 357 CLK_ROOT_POST_DIV17, 358 CLK_ROOT_POST_DIV18, 359 CLK_ROOT_POST_DIV19, 360 CLK_ROOT_POST_DIV20, 361 CLK_ROOT_POST_DIV21, 362 CLK_ROOT_POST_DIV22, 363 CLK_ROOT_POST_DIV23, 364 CLK_ROOT_POST_DIV24, 365 CLK_ROOT_POST_DIV25, 366 CLK_ROOT_POST_DIV26, 367 CLK_ROOT_POST_DIV27, 368 CLK_ROOT_POST_DIV28, 369 CLK_ROOT_POST_DIV29, 370 CLK_ROOT_POST_DIV30, 371 CLK_ROOT_POST_DIV31, 372 CLK_ROOT_POST_DIV32, 373 CLK_ROOT_POST_DIV33, 374 CLK_ROOT_POST_DIV34, 375 CLK_ROOT_POST_DIV35, 376 CLK_ROOT_POST_DIV36, 377 CLK_ROOT_POST_DIV37, 378 CLK_ROOT_POST_DIV38, 379 CLK_ROOT_POST_DIV39, 380 CLK_ROOT_POST_DIV40, 381 CLK_ROOT_POST_DIV41, 382 CLK_ROOT_POST_DIV42, 383 CLK_ROOT_POST_DIV43, 384 CLK_ROOT_POST_DIV44, 385 CLK_ROOT_POST_DIV45, 386 CLK_ROOT_POST_DIV46, 387 CLK_ROOT_POST_DIV47, 388 CLK_ROOT_POST_DIV48, 389 CLK_ROOT_POST_DIV49, 390 CLK_ROOT_POST_DIV50, 391 CLK_ROOT_POST_DIV51, 392 CLK_ROOT_POST_DIV52, 393 CLK_ROOT_POST_DIV53, 394 CLK_ROOT_POST_DIV54, 395 CLK_ROOT_POST_DIV55, 396 CLK_ROOT_POST_DIV56, 397 CLK_ROOT_POST_DIV57, 398 CLK_ROOT_POST_DIV58, 399 CLK_ROOT_POST_DIV59, 400 CLK_ROOT_POST_DIV60, 401 CLK_ROOT_POST_DIV61, 402 CLK_ROOT_POST_DIV62, 403 CLK_ROOT_POST_DIV63, 404 CLK_ROOT_POST_DIV64, 405 }; 406 407 struct clk_root_map { 408 enum clk_root_index entry; 409 enum clk_slice_type slice_type; 410 u32 slice_index; 411 u8 src_mux[8]; 412 }; 413 414 struct ccm_ccgr { 415 u32 ccgr; 416 u32 ccgr_set; 417 u32 ccgr_clr; 418 u32 ccgr_tog; 419 }; 420 421 struct ccm_root { 422 u32 target_root; 423 u32 target_root_set; 424 u32 target_root_clr; 425 u32 target_root_tog; 426 u32 misc; 427 u32 misc_set; 428 u32 misc_clr; 429 u32 misc_tog; 430 u32 nm_post; 431 u32 nm_post_root_set; 432 u32 nm_post_root_clr; 433 u32 nm_post_root_tog; 434 u32 nm_pre; 435 u32 nm_pre_root_set; 436 u32 nm_pre_root_clr; 437 u32 nm_pre_root_tog; 438 u32 db_post; 439 u32 db_post_root_set; 440 u32 db_post_root_clr; 441 u32 db_post_root_tog; 442 u32 db_pre; 443 u32 db_pre_root_set; 444 u32 db_pre_root_clr; 445 u32 db_pre_root_tog; 446 u32 reserved[4]; 447 u32 access_ctrl; 448 u32 access_ctrl_root_set; 449 u32 access_ctrl_root_clr; 450 u32 access_ctrl_root_tog; 451 }; 452 453 struct ccm_reg { 454 u32 reserved_0[4096]; 455 struct ccm_ccgr ccgr_array[192]; 456 u32 reserved_1[3328]; 457 struct ccm_root core_root[5]; 458 u32 reserved_2[352]; 459 struct ccm_root bus_root[12]; 460 u32 reserved_3[128]; 461 struct ccm_root ahb_ipg_root[4]; 462 u32 reserved_4[384]; 463 struct ccm_root dram_sel; 464 struct ccm_root core_sel; 465 u32 reserved_5[448]; 466 struct ccm_root ip_root[78]; 467 }; 468 469 #define CCGR_CLK_ON_MASK 0x03 470 #define CLK_SRC_ON_MASK 0x03 471 472 #define CLK_ROOT_ON BIT(28) 473 #define CLK_ROOT_OFF (0 << 28) 474 #define CLK_ROOT_ENABLE_MASK BIT(28) 475 #define CLK_ROOT_ENABLE_SHIFT 28 476 #define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24) 477 478 /* For SEL, only use 1 bit */ 479 #define CLK_ROOT_SRC_MUX_MASK 0x07000000 480 #define CLK_ROOT_SRC_MUX_SHIFT 24 481 #define CLK_ROOT_SRC_0 0x00000000 482 #define CLK_ROOT_SRC_1 0x01000000 483 #define CLK_ROOT_SRC_2 0x02000000 484 #define CLK_ROOT_SRC_3 0x03000000 485 #define CLK_ROOT_SRC_4 0x04000000 486 #define CLK_ROOT_SRC_5 0x05000000 487 #define CLK_ROOT_SRC_6 0x06000000 488 #define CLK_ROOT_SRC_7 0x07000000 489 490 #define CLK_ROOT_PRE_DIV_MASK (0x00070000) 491 #define CLK_ROOT_PRE_DIV_SHIFT 16 492 #define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000) 493 494 #define CLK_ROOT_AUDO_SLOW_EN 0x1000 495 496 #define CLK_ROOT_AUDO_DIV_MASK 0x700 497 #define CLK_ROOT_AUDO_DIV_SHIFT 0x8 498 #define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700) 499 500 /* For CORE: mask is 0x7; For IPG: mask is 0x3 */ 501 #define CLK_ROOT_POST_DIV_MASK 0x3f 502 #define CLK_ROOT_CORE_POST_DIV_MASK 0x7 503 #define CLK_ROOT_IPG_POST_DIV_MASK 0x3 504 #define CLK_ROOT_POST_DIV_SHIFT 0 505 #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) 506 507 /* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ 508 #define FRAC_PLL_LOCK_MASK BIT(31) 509 #define FRAC_PLL_CLKE_MASK BIT(21) 510 #define FRAC_PLL_PD_MASK BIT(19) 511 #define FRAC_PLL_REFCLK_SEL_MASK BIT(16) 512 #define FRAC_PLL_LOCK_SEL_MASK BIT(15) 513 #define FRAC_PLL_BYPASS_MASK BIT(14) 514 #define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) 515 #define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) 516 #define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) 517 #define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) 518 #define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) 519 #define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 520 #define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f 521 #define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f) 522 523 #define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) 524 #define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) 525 #define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) 526 #define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16) 527 528 #define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) 529 #define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 530 #define FRAC_PLL_INT_DIV_CTL_MASK 0x7f 531 #define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) 532 533 /* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ 534 #define SSCG_PLL_LOCK_MASK BIT(31) 535 #define SSCG_PLL_CLKE_MASK BIT(25) 536 #define SSCG_PLL_DIV2_CLKE_MASK BIT(23) 537 #define SSCG_PLL_DIV3_CLKE_MASK BIT(21) 538 #define SSCG_PLL_DIV4_CLKE_MASK BIT(19) 539 #define SSCG_PLL_DIV5_CLKE_MASK BIT(17) 540 #define SSCG_PLL_DIV6_CLKE_MASK BIT(15) 541 #define SSCG_PLL_DIV8_CLKE_MASK BIT(13) 542 #define SSCG_PLL_DIV10_CLKE_MASK BIT(11) 543 #define SSCG_PLL_DIV20_CLKE_MASK BIT(9) 544 #define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) 545 #define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) 546 #define SSCG_PLL_PLL3_CLKE_MASK BIT(9) 547 #define SSCG_PLL_PD_MASK BIT(7) 548 #define SSCG_PLL_BYPASS1_MASK BIT(5) 549 #define SSCG_PLL_BYPASS2_MASK BIT(4) 550 #define SSCG_PLL_LOCK_SEL_MASK BIT(3) 551 #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) 552 #define SSCG_PLL_REFCLK_SEL_MASK 0x3 553 #define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) 554 #define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) 555 #define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) 556 #define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) 557 558 #define SSCG_PLL_SSDS_MASK BIT(8) 559 #define SSCG_PLL_SSMD_MASK (0x7 << 5) 560 #define SSCG_PLL_SSMF_MASK (0xf << 1) 561 #define SSCG_PLL_SSE_MASK 0x1 562 563 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) 564 #define SSCG_PLL_REF_DIVR1_SHIFT 25 565 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) 566 #define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) 567 #define SSCG_PLL_REF_DIVR2_SHIFT 19 568 #define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) 569 #define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) 570 #define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 571 #define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ 572 SSCG_PLL_FEEDBACK_DIV_F1_MASK) 573 #define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) 574 #define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 575 #define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ 576 SSCG_PLL_FEEDBACK_DIV_F2_MASK) 577 #define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) 578 #define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 579 #define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ 580 SSCG_PLL_OUTPUT_DIV_VAL_MASK) 581 #define SSCG_PLL_FILTER_RANGE_MASK 0x1 582 583 #define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) 584 #define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) 585 #define HW_DIGPROG_MINOR_MASK 0xff 586 587 #define HW_OSC_27M_CLKE_MASK BIT(4) 588 #define HW_OSC_25M_CLKE_MASK BIT(2) 589 #define HW_OSC_32K_SEL_MASK 0x1 590 #define HW_OSC_32K_SEL_RTC 0x1 591 #define HW_OSC_32K_SEL_25M_DIV800 0x0 592 593 #define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) 594 #define HW_FRAC_ARM_PLL_DIV_SHIFT 20 595 #define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) 596 #define HW_FRAC_VPU_PLL_DIV_SHIFT 16 597 #define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) 598 #define HW_FRAC_GPU_PLL_DIV_SHIFT 12 599 #define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) 600 #define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 601 #define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) 602 #define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 603 #define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 604 #define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0 605 606 #define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) 607 #define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 608 #define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) 609 #define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 610 #define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) 611 #define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 612 #define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) 613 #define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 614 #define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 615 #define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0 616 617 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 618 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 619 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 620 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 621 #define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000 622 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 623 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 624 625 enum enet_freq { 626 ENET_25MHZ = 0, 627 ENET_50MHZ, 628 ENET_125MHZ, 629 }; 630 631 enum frac_pll_out_val { 632 FRAC_PLL_OUT_1000M, 633 FRAC_PLL_OUT_1600M, 634 }; 635 636 #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ 637 { \ 638 .clk = (_rate), \ 639 .alt_root_sel = (_m), \ 640 .alt_pre_div = (_p), \ 641 .apb_root_sel = (_s), \ 642 .apb_pre_div = (_k), \ 643 } 644 645 struct dram_bypass_clk_setting { 646 ulong clk; 647 int alt_root_sel; 648 enum root_pre_div alt_pre_div; 649 int apb_root_sel; 650 enum root_pre_div apb_pre_div; 651 }; 652 653 void dram_pll_init(ulong pll_val); 654 void dram_enable_bypass(ulong clk_val); 655 void dram_disable_bypass(void); 656 u32 imx_get_fecclk(void); 657 u32 imx_get_uartclk(void); 658 int clock_init(void); 659 void init_clk_usdhc(u32 index); 660 void init_uart_clk(u32 index); 661 void init_wdog_clk(void); 662 unsigned int mxc_get_clock(enum clk_root_index clk); 663 int clock_enable(enum clk_ccgr_index index, bool enable); 664 int clock_root_enabled(enum clk_root_index clock_id); 665 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, 666 enum root_post_div post_div, enum clk_root_src clock_src); 667 int clock_set_target_val(enum clk_root_index clock_id, u32 val); 668 int clock_get_target_val(enum clk_root_index clock_id, u32 *val); 669 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); 670 int clock_get_postdiv(enum clk_root_index clock_id, 671 enum root_post_div *post_div); 672 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); 673 void mxs_set_lcdclk(u32 base_addr, u32 freq); 674 int set_clk_qspi(void); 675 void enable_ocotp_clk(unsigned char enable); 676 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); 677 int set_clk_enet(enum enet_freq type); 678 #endif 679