1 /* 2 * (C) Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #define MXC_CPU_MX23 0x23 8 #define MXC_CPU_MX25 0x25 9 #define MXC_CPU_MX27 0x27 10 #define MXC_CPU_MX28 0x28 11 #define MXC_CPU_MX31 0x31 12 #define MXC_CPU_MX35 0x35 13 #define MXC_CPU_MX51 0x51 14 #define MXC_CPU_MX53 0x53 15 #define MXC_CPU_MX6SL 0x60 16 #define MXC_CPU_MX6DL 0x61 17 #define MXC_CPU_MX6SX 0x62 18 #define MXC_CPU_MX6Q 0x63 19 #define MXC_CPU_MX6UL 0x64 20 #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ 21 #define MXC_CPU_MX6D 0x67 22 #define MXC_CPU_MX6DP 0x68 23 #define MXC_CPU_MX6QP 0x69 24 #define MXC_CPU_MX7D 0x72 25 #define MXC_CPU_VF610 0xF6 /* dummy ID */ 26 27 #define MXC_SOC_MX6 0x60 28 #define MXC_SOC_MX7 0x70 29 30 #define CHIP_REV_1_0 0x10 31 #define CHIP_REV_1_1 0x11 32 #define CHIP_REV_1_2 0x12 33 #define CHIP_REV_1_5 0x15 34 #define CHIP_REV_2_0 0x20 35 #define CHIP_REV_2_5 0x25 36 #define CHIP_REV_3_0 0x30 37 38 #define BOARD_REV_1_0 0x0 39 #define BOARD_REV_2_0 0x1 40 #define BOARD_VER_OFFSET 0x8 41 42 #define CS0_128 0 43 #define CS0_64M_CS1_64M 1 44 #define CS0_64M_CS1_32M_CS2_32M 2 45 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 46 47 u32 get_imx_reset_cause(void); 48