1 /* 2 * (C) Copyright 2017 Linaro 3 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __HI3798cv200_H__ 9 #define __HI3798cv200_H__ 10 11 #define REG_BASE_PERI_CTRL 0xF8A20000 12 #define REG_BASE_CRG 0xF8A22000 13 14 /* DEVICES */ 15 #define REG_BASE_MCI 0xF9830000 16 #define REG_BASE_UART0 0xF8B00000 17 18 /* PERI control registers (4KB) */ 19 /* USB2 PHY01 configuration register */ 20 #define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) 21 22 /* PERI CRG registers (4KB) */ 23 /* USB2 CTRL0 clock and soft reset */ 24 #define PERI_CRG46 (REG_BASE_CRG + 0xb8) 25 #define USB2_BUS_CKEN (1<<0) 26 #define USB2_OHCI48M_CKEN (1<<1) 27 #define USB2_OHCI12M_CKEN (1<<2) 28 #define USB2_OTG_UTMI_CKEN (1<<3) 29 #define USB2_HST_PHY_CKEN (1<<4) 30 #define USB2_UTMI0_CKEN (1<<5) 31 #define USB2_BUS_SRST_REQ (1<<12) 32 #define USB2_UTMI0_SRST_REQ (1<<13) 33 #define USB2_HST_PHY_SYST_REQ (1<<16) 34 #define USB2_OTG_PHY_SYST_REQ (1<<17) 35 #define USB2_CLK48_SEL (1<<20) 36 37 /* USB2 PHY clock and soft reset */ 38 #define PERI_CRG47 (REG_BASE_CRG + 0xbc) 39 #define USB2_PHY01_REF_CKEN (1 << 0) 40 #define USB2_PHY2_REF_CKEN (1 << 2) 41 #define USB2_PHY01_SRST_REQ (1 << 4) 42 #define USB2_PHY2_SRST_REQ (1 << 6) 43 #define USB2_PHY01_SRST_TREQ0 (1 << 8) 44 #define USB2_PHY01_SRST_TREQ1 (1 << 9) 45 #define USB2_PHY2_SRST_TREQ (1 << 10) 46 #define USB2_PHY01_REFCLK_SEL (1 << 12) 47 #define USB2_PHY2_REFCLK_SEL (1 << 14) 48 49 50 #endif 51