1 /* 2 * Copyright 2017 NXP Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 */ 7 #ifndef __FSL_STREAM_ID_H 8 #define __FSL_STREAM_ID_H 9 10 /* 11 * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices 12 * are not hardwired and are programmed by sw. There are a limited number 13 * of stream IDs available, and the partitioning of them is scenario 14 * dependent. This header defines the partitioning between legacy, PCI, 15 * and DPAA1 devices. 16 * 17 * This partitioning can be customized in this file depending 18 * on the specific hardware config: 19 * 20 * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) 21 * -all legacy devices get a unique stream ID assigned and programmed in 22 * their AMQR registers by u-boot 23 * 24 * -PCIe 25 * -there is a range of stream IDs set aside for PCI in this 26 * file. U-boot will scan the PCI bus and for each device discovered: 27 * -allocate a streamID 28 * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' 29 * -set a msi-map entry in the PEXn controller node in the 30 * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt 31 * for more info on the msi-map definition) 32 * -set a iommu-map entry in the PEXn controller node in the 33 * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt 34 * for more info on the iommu-map definition) 35 * 36 * -DPAA1 37 * - Stream ids for DPAA1 use are reserved for future usecase. 38 * 39 */ 40 41 42 #define FSL_INVALID_STREAM_ID 0 43 44 /* legacy devices */ 45 #define FSL_USB1_STREAM_ID 1 46 #define FSL_USB2_STREAM_ID 2 47 #define FSL_USB3_STREAM_ID 3 48 #define FSL_SDHC_STREAM_ID 4 49 #define FSL_SATA_STREAM_ID 5 50 #define FSL_QE_STREAM_ID 6 51 #define FSL_QDMA_STREAM_ID 7 52 #define FSL_EDMA_STREAM_ID 8 53 #define FSL_ETR_STREAM_ID 9 54 55 /* PCI - programmed in PEXn_LUT */ 56 #define FSL_PEX_STREAM_ID_START 11 57 #define FSL_PEX_STREAM_ID_END 26 58 59 /* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ 60 #define FSL_DPAA1_STREAM_ID_START 27 61 #define FSL_DPAA1_STREAM_ID_END 63 62 63 #endif 64