1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9 10 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 11 #define gur_in32(a) in_le32(a) 12 #define gur_out32(a, v) out_le32(a, v) 13 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 14 #define gur_in32(a) in_be32(a) 15 #define gur_out32(a, v) out_be32(a, v) 16 #endif 17 18 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 19 #define scfg_in32(a) in_le32(a) 20 #define scfg_out32(a, v) out_le32(a, v) 21 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 22 #define scfg_in32(a) in_be32(a) 23 #define scfg_out32(a, v) out_be32(a, v) 24 #endif 25 26 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 27 #define pex_lut_in32(a) in_le32(a) 28 #define pex_lut_out32(a, v) out_le32(a, v) 29 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 30 #define pex_lut_in32(a) in_be32(a) 31 #define pex_lut_out32(a, v) out_be32(a, v) 32 #endif 33 #ifndef __ASSEMBLY__ 34 struct cpu_type { 35 char name[15]; 36 u32 soc_ver; 37 u32 num_cores; 38 }; 39 40 #define CPU_TYPE_ENTRY(n, v, nc) \ 41 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 42 #endif 43 #define SVR_WO_E 0xFFFFFE 44 #define SVR_LS1012A 0x870400 45 #define SVR_LS1043A 0x879200 46 #define SVR_LS1023A 0x879208 47 #define SVR_LS1046A 0x870700 48 #define SVR_LS1026A 0x870708 49 #define SVR_LS2045A 0x870120 50 #define SVR_LS2080A 0x870110 51 #define SVR_LS2085A 0x870100 52 #define SVR_LS2040A 0x870130 53 #define SVR_LS2088A 0x870900 54 #define SVR_LS2084A 0x870910 55 #define SVR_LS2048A 0x870920 56 #define SVR_LS2044A 0x870930 57 58 #define SVR_DEV_LS2080A 0x8701 59 60 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 61 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 62 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 63 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 64 #define IS_SVR_REV(svr, maj, min) \ 65 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 66 67 /* ahci port register default value */ 68 #define AHCI_PORT_PHY_1_CFG 0xa003fffe 69 #define AHCI_PORT_TRANS_CFG 0x08000029 70 #define AHCI_PORT_AXICC_CFG 0x3fffffff 71 72 #ifndef __ASSEMBLY__ 73 /* AHCI (sata) register map */ 74 struct ccsr_ahci { 75 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 76 u32 pcfg; /* port config */ 77 u32 ppcfg; /* port phy1 config */ 78 u32 pp2c; /* port phy2 config */ 79 u32 pp3c; /* port phy3 config */ 80 u32 pp4c; /* port phy4 config */ 81 u32 pp5c; /* port phy5 config */ 82 u32 axicc; /* AXI cache control */ 83 u32 paxic; /* port AXI config */ 84 u32 axipc; /* AXI PROT control */ 85 u32 ptc; /* port Trans Config */ 86 u32 pts; /* port Trans Status */ 87 u32 plc; /* port link config */ 88 u32 plc1; /* port link config1 */ 89 u32 plc2; /* port link config2 */ 90 u32 pls; /* port link status */ 91 u32 pls1; /* port link status1 */ 92 u32 pcmdc; /* port CMD config */ 93 u32 ppcs; /* port phy control status */ 94 u32 pberr; /* port 0/1 BIST error */ 95 u32 cmds; /* port 0/1 CMD status error */ 96 }; 97 98 #ifdef CONFIG_FSL_LSCH3 99 void fsl_lsch3_early_init_f(void); 100 #elif defined(CONFIG_FSL_LSCH2) 101 void fsl_lsch2_early_init_f(void); 102 #endif 103 104 void cpu_name(char *name); 105 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 106 void erratum_a009635(void); 107 #endif 108 109 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 110 void erratum_a010315(void); 111 #endif 112 113 bool soc_has_dp_ddr(void); 114 bool soc_has_aiop(void); 115 #endif 116 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 117