1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 10 11 #ifndef __ASSEMBLY__ 12 #include <linux/types.h> 13 #ifdef CONFIG_FSL_LSCH2 14 #include <asm/arch/immap_lsch2.h> 15 #endif 16 #ifdef CONFIG_FSL_LSCH3 17 #include <asm/arch/immap_lsch3.h> 18 #endif 19 #endif 20 21 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 22 #define gur_in32(a) in_le32(a) 23 #define gur_out32(a, v) out_le32(a, v) 24 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 25 #define gur_in32(a) in_be32(a) 26 #define gur_out32(a, v) out_be32(a, v) 27 #endif 28 29 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 30 #define scfg_in32(a) in_le32(a) 31 #define scfg_out32(a, v) out_le32(a, v) 32 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 33 #define scfg_in32(a) in_be32(a) 34 #define scfg_out32(a, v) out_be32(a, v) 35 #endif 36 37 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 38 #define pex_lut_in32(a) in_le32(a) 39 #define pex_lut_out32(a, v) out_le32(a, v) 40 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 41 #define pex_lut_in32(a) in_be32(a) 42 #define pex_lut_out32(a, v) out_be32(a, v) 43 #endif 44 #ifndef __ASSEMBLY__ 45 struct cpu_type { 46 char name[15]; 47 u32 soc_ver; 48 u32 num_cores; 49 }; 50 51 #define CPU_TYPE_ENTRY(n, v, nc) \ 52 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 53 #endif 54 #define SVR_WO_E 0xFFFFFE 55 #define SVR_LS1012A 0x870400 56 #define SVR_LS1043A 0x879200 57 #define SVR_LS1023A 0x879208 58 #define SVR_LS1046A 0x870700 59 #define SVR_LS1026A 0x870708 60 #define SVR_LS2045A 0x870120 61 #define SVR_LS2080A 0x870110 62 #define SVR_LS2085A 0x870100 63 #define SVR_LS2040A 0x870130 64 #define SVR_LS2088A 0x870900 65 #define SVR_LS2084A 0x870910 66 #define SVR_LS2048A 0x870920 67 #define SVR_LS2044A 0x870930 68 #define SVR_LS2081A 0x870918 69 #define SVR_LS2041A 0x870914 70 71 #define SVR_DEV_LS2080A 0x8701 72 73 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 74 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 75 #define SVR_REV(svr) (((svr) >> 0) & 0xff) 76 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 77 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 78 #define IS_SVR_REV(svr, maj, min) \ 79 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 80 81 /* ahci port register default value */ 82 #define AHCI_PORT_PHY_1_CFG 0xa003fffe 83 #define AHCI_PORT_TRANS_CFG 0x08000029 84 #define AHCI_PORT_AXICC_CFG 0x3fffffff 85 86 #ifndef __ASSEMBLY__ 87 /* AHCI (sata) register map */ 88 struct ccsr_ahci { 89 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 90 u32 pcfg; /* port config */ 91 u32 ppcfg; /* port phy1 config */ 92 u32 pp2c; /* port phy2 config */ 93 u32 pp3c; /* port phy3 config */ 94 u32 pp4c; /* port phy4 config */ 95 u32 pp5c; /* port phy5 config */ 96 u32 axicc; /* AXI cache control */ 97 u32 paxic; /* port AXI config */ 98 u32 axipc; /* AXI PROT control */ 99 u32 ptc; /* port Trans Config */ 100 u32 pts; /* port Trans Status */ 101 u32 plc; /* port link config */ 102 u32 plc1; /* port link config1 */ 103 u32 plc2; /* port link config2 */ 104 u32 pls; /* port link status */ 105 u32 pls1; /* port link status1 */ 106 u32 pcmdc; /* port CMD config */ 107 u32 ppcs; /* port phy control status */ 108 u32 pberr; /* port 0/1 BIST error */ 109 u32 cmds; /* port 0/1 CMD status error */ 110 }; 111 112 #ifdef CONFIG_FSL_LSCH3 113 void fsl_lsch3_early_init_f(void); 114 #elif defined(CONFIG_FSL_LSCH2) 115 void fsl_lsch2_early_init_f(void); 116 int setup_chip_volt(void); 117 /* Setup core vdd in unit mV */ 118 int board_setup_core_volt(u32 vdd); 119 #endif 120 121 void cpu_name(char *name); 122 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 123 void erratum_a009635(void); 124 #endif 125 126 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 127 void erratum_a010315(void); 128 #endif 129 130 bool soc_has_dp_ddr(void); 131 bool soc_has_aiop(void); 132 #endif 133 134 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 135