1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 10 11 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 12 #define gur_in32(a) in_le32(a) 13 #define gur_out32(a, v) out_le32(a, v) 14 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 15 #define gur_in32(a) in_be32(a) 16 #define gur_out32(a, v) out_be32(a, v) 17 #endif 18 19 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 20 #define scfg_in32(a) in_le32(a) 21 #define scfg_out32(a, v) out_le32(a, v) 22 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 23 #define scfg_in32(a) in_be32(a) 24 #define scfg_out32(a, v) out_be32(a, v) 25 #endif 26 27 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 28 #define pex_lut_in32(a) in_le32(a) 29 #define pex_lut_out32(a, v) out_le32(a, v) 30 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 31 #define pex_lut_in32(a) in_be32(a) 32 #define pex_lut_out32(a, v) out_be32(a, v) 33 #endif 34 #ifndef __ASSEMBLY__ 35 struct cpu_type { 36 char name[15]; 37 u32 soc_ver; 38 u32 num_cores; 39 }; 40 41 #define CPU_TYPE_ENTRY(n, v, nc) \ 42 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 43 #endif 44 #define SVR_WO_E 0xFFFFFE 45 #define SVR_LS1012A 0x870400 46 #define SVR_LS1043A 0x879200 47 #define SVR_LS1023A 0x879208 48 #define SVR_LS1046A 0x870700 49 #define SVR_LS1026A 0x870708 50 #define SVR_LS2045A 0x870120 51 #define SVR_LS2080A 0x870110 52 #define SVR_LS2085A 0x870100 53 #define SVR_LS2040A 0x870130 54 #define SVR_LS2088A 0x870900 55 #define SVR_LS2084A 0x870910 56 #define SVR_LS2048A 0x870920 57 #define SVR_LS2044A 0x870930 58 #define SVR_LS2081A 0x870919 59 #define SVR_LS2041A 0x870915 60 61 #define SVR_DEV_LS2080A 0x8701 62 63 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 64 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 65 #define SVR_REV(svr) (((svr) >> 0) & 0xff) 66 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 67 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 68 #define IS_SVR_REV(svr, maj, min) \ 69 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 70 71 /* ahci port register default value */ 72 #define AHCI_PORT_PHY_1_CFG 0xa003fffe 73 #define AHCI_PORT_TRANS_CFG 0x08000029 74 #define AHCI_PORT_AXICC_CFG 0x3fffffff 75 76 #ifndef __ASSEMBLY__ 77 /* AHCI (sata) register map */ 78 struct ccsr_ahci { 79 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 80 u32 pcfg; /* port config */ 81 u32 ppcfg; /* port phy1 config */ 82 u32 pp2c; /* port phy2 config */ 83 u32 pp3c; /* port phy3 config */ 84 u32 pp4c; /* port phy4 config */ 85 u32 pp5c; /* port phy5 config */ 86 u32 axicc; /* AXI cache control */ 87 u32 paxic; /* port AXI config */ 88 u32 axipc; /* AXI PROT control */ 89 u32 ptc; /* port Trans Config */ 90 u32 pts; /* port Trans Status */ 91 u32 plc; /* port link config */ 92 u32 plc1; /* port link config1 */ 93 u32 plc2; /* port link config2 */ 94 u32 pls; /* port link status */ 95 u32 pls1; /* port link status1 */ 96 u32 pcmdc; /* port CMD config */ 97 u32 ppcs; /* port phy control status */ 98 u32 pberr; /* port 0/1 BIST error */ 99 u32 cmds; /* port 0/1 CMD status error */ 100 }; 101 102 #ifdef CONFIG_FSL_LSCH3 103 void fsl_lsch3_early_init_f(void); 104 #elif defined(CONFIG_FSL_LSCH2) 105 void fsl_lsch2_early_init_f(void); 106 int setup_chip_volt(void); 107 /* Setup core vdd in unit mV */ 108 int board_setup_core_volt(u32 vdd); 109 #endif 110 111 void cpu_name(char *name); 112 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 113 void erratum_a009635(void); 114 #endif 115 116 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 117 void erratum_a010315(void); 118 #endif 119 120 bool soc_has_dp_ddr(void); 121 bool soc_has_aiop(void); 122 #endif 123 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 124