1 /* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9 10 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 11 #define gur_in32(a) in_le32(a) 12 #define gur_out32(a, v) out_le32(a, v) 13 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 14 #define gur_in32(a) in_be32(a) 15 #define gur_out32(a, v) out_be32(a, v) 16 #endif 17 18 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 19 #define scfg_in32(a) in_le32(a) 20 #define scfg_out32(a, v) out_le32(a, v) 21 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 22 #define scfg_in32(a) in_be32(a) 23 #define scfg_out32(a, v) out_be32(a, v) 24 #endif 25 26 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 27 #define pex_lut_in32(a) in_le32(a) 28 #define pex_lut_out32(a, v) out_le32(a, v) 29 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 30 #define pex_lut_in32(a) in_be32(a) 31 #define pex_lut_out32(a, v) out_be32(a, v) 32 #endif 33 34 struct cpu_type { 35 char name[15]; 36 u32 soc_ver; 37 u32 num_cores; 38 }; 39 40 #define CPU_TYPE_ENTRY(n, v, nc) \ 41 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 42 43 #define SVR_WO_E 0xFFFFFE 44 #define SVR_LS1043 0x879204 45 #define SVR_LS2045 0x870120 46 #define SVR_LS2080 0x870110 47 #define SVR_LS2085 0x870100 48 49 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 50 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 51 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 52 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 53 54 #ifdef CONFIG_FSL_LSCH3 55 void fsl_lsch3_early_init_f(void); 56 #elif defined(CONFIG_FSL_LSCH2) 57 void fsl_lsch2_early_init_f(void); 58 #endif 59 60 void cpu_name(char *name); 61 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 62 void erratum_a009635(void); 63 #endif 64 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 65