1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
9 
10 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
11 #define gur_in32(a)       in_le32(a)
12 #define gur_out32(a, v)   out_le32(a, v)
13 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
14 #define gur_in32(a)       in_be32(a)
15 #define gur_out32(a, v)   out_be32(a, v)
16 #endif
17 
18 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
19 #define scfg_in32(a)       in_le32(a)
20 #define scfg_out32(a, v)   out_le32(a, v)
21 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
22 #define scfg_in32(a)       in_be32(a)
23 #define scfg_out32(a, v)   out_be32(a, v)
24 #endif
25 
26 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE
27 #define pex_lut_in32(a)       in_le32(a)
28 #define pex_lut_out32(a, v)   out_le32(a, v)
29 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
30 #define pex_lut_in32(a)       in_be32(a)
31 #define pex_lut_out32(a, v)   out_be32(a, v)
32 #endif
33 
34 struct cpu_type {
35 	char name[15];
36 	u32 soc_ver;
37 	u32 num_cores;
38 };
39 
40 #define CPU_TYPE_ENTRY(n, v, nc) \
41 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
42 
43 #define SVR_WO_E		0xFFFFFE
44 #define SVR_LS1012		0x870400
45 #define SVR_LS1043		0x879200
46 #define SVR_LS1023		0x879208
47 #define SVR_LS2045		0x870120
48 #define SVR_LS2080		0x870110
49 #define SVR_LS2085		0x870100
50 #define SVR_LS2040		0x870130
51 
52 #define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
53 #define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
54 #define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
55 #define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
56 
57 /* ahci port register default value */
58 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
59 #define AHCI_PORT_PHY_2_CFG    0x28184d1f
60 #define AHCI_PORT_PHY_3_CFG    0x0e081509
61 #define AHCI_PORT_TRANS_CFG    0x08000029
62 
63 /* AHCI (sata) register map */
64 struct ccsr_ahci {
65 	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
66 	u32 pcfg;	/* port config */
67 	u32 ppcfg;	/* port phy1 config */
68 	u32 pp2c;	/* port phy2 config */
69 	u32 pp3c;	/* port phy3 config */
70 	u32 pp4c;	/* port phy4 config */
71 	u32 pp5c;	/* port phy5 config */
72 	u32 axicc;	/* AXI cache control */
73 	u32 paxic;	/* port AXI config */
74 	u32 axipc;	/* AXI PROT control */
75 	u32 ptc;	/* port Trans Config */
76 	u32 pts;	/* port Trans Status */
77 	u32 plc;	/* port link config */
78 	u32 plc1;	/* port link config1 */
79 	u32 plc2;	/* port link config2 */
80 	u32 pls;	/* port link status */
81 	u32 pls1;	/* port link status1 */
82 	u32 pcmdc;	/* port CMD config */
83 	u32 ppcs;	/* port phy control status */
84 	u32 pberr;	/* port 0/1 BIST error */
85 	u32 cmds;	/* port 0/1 CMD status error */
86 };
87 
88 #ifdef CONFIG_FSL_LSCH3
89 void fsl_lsch3_early_init_f(void);
90 #elif defined(CONFIG_FSL_LSCH2)
91 void fsl_lsch2_early_init_f(void);
92 #endif
93 
94 void cpu_name(char *name);
95 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
96 void erratum_a009635(void);
97 #endif
98 
99 bool soc_has_dp_ddr(void);
100 bool soc_has_aiop(void);
101 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
102