1 /* 2 * Copyright 2017 NXP 3 * Copyright 2015 Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 9 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ 10 11 #ifndef __ASSEMBLY__ 12 #include <linux/types.h> 13 #ifdef CONFIG_FSL_LSCH2 14 #include <asm/arch/immap_lsch2.h> 15 #endif 16 #ifdef CONFIG_FSL_LSCH3 17 #include <asm/arch/immap_lsch3.h> 18 #endif 19 #endif 20 21 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE 22 #define gur_in32(a) in_le32(a) 23 #define gur_out32(a, v) out_le32(a, v) 24 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) 25 #define gur_in32(a) in_be32(a) 26 #define gur_out32(a, v) out_be32(a, v) 27 #endif 28 29 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE 30 #define scfg_in32(a) in_le32(a) 31 #define scfg_out32(a, v) out_le32(a, v) 32 #define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear) 33 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set) 34 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) 35 #define scfg_in32(a) in_be32(a) 36 #define scfg_out32(a, v) out_be32(a, v) 37 #define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear) 38 #define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set) 39 #endif 40 41 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE 42 #define pex_lut_in32(a) in_le32(a) 43 #define pex_lut_out32(a, v) out_le32(a, v) 44 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE) 45 #define pex_lut_in32(a) in_be32(a) 46 #define pex_lut_out32(a, v) out_be32(a, v) 47 #endif 48 #ifndef __ASSEMBLY__ 49 struct cpu_type { 50 char name[15]; 51 u32 soc_ver; 52 u32 num_cores; 53 }; 54 55 #define CPU_TYPE_ENTRY(n, v, nc) \ 56 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} 57 #endif 58 #define SVR_WO_E 0xFFFFFE 59 #define SVR_LS1012A 0x870400 60 #define SVR_LS1043A 0x879200 61 #define SVR_LS1023A 0x879208 62 #define SVR_LS1046A 0x870700 63 #define SVR_LS1026A 0x870708 64 #define SVR_LS1048A 0x870320 65 #define SVR_LS1084A 0x870302 66 #define SVR_LS1088A 0x870300 67 #define SVR_LS1044A 0x870322 68 #define SVR_LS2045A 0x870120 69 #define SVR_LS2080A 0x870110 70 #define SVR_LS2085A 0x870100 71 #define SVR_LS2040A 0x870130 72 #define SVR_LS2088A 0x870900 73 #define SVR_LS2084A 0x870910 74 #define SVR_LS2048A 0x870920 75 #define SVR_LS2044A 0x870930 76 #define SVR_LS2081A 0x870918 77 #define SVR_LS2041A 0x870914 78 79 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) 80 #define SVR_MIN(svr) (((svr) >> 0) & 0xf) 81 #define SVR_REV(svr) (((svr) >> 0) & 0xff) 82 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) 83 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) 84 #define IS_SVR_REV(svr, maj, min) \ 85 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) 86 #define SVR_DEV(svr) ((svr) >> 8) 87 #define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev)) 88 89 /* ahci port register default value */ 90 #define AHCI_PORT_PHY_1_CFG 0xa003fffe 91 #define AHCI_PORT_PHY2_CFG 0x28184d1f 92 #define AHCI_PORT_PHY3_CFG 0x0e081509 93 #define AHCI_PORT_TRANS_CFG 0x08000029 94 #define AHCI_PORT_AXICC_CFG 0x3fffffff 95 96 #ifndef __ASSEMBLY__ 97 /* AHCI (sata) register map */ 98 struct ccsr_ahci { 99 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ 100 u32 pcfg; /* port config */ 101 u32 ppcfg; /* port phy1 config */ 102 u32 pp2c; /* port phy2 config */ 103 u32 pp3c; /* port phy3 config */ 104 u32 pp4c; /* port phy4 config */ 105 u32 pp5c; /* port phy5 config */ 106 u32 axicc; /* AXI cache control */ 107 u32 paxic; /* port AXI config */ 108 u32 axipc; /* AXI PROT control */ 109 u32 ptc; /* port Trans Config */ 110 u32 pts; /* port Trans Status */ 111 u32 plc; /* port link config */ 112 u32 plc1; /* port link config1 */ 113 u32 plc2; /* port link config2 */ 114 u32 pls; /* port link status */ 115 u32 pls1; /* port link status1 */ 116 u32 pcmdc; /* port CMD config */ 117 u32 ppcs; /* port phy control status */ 118 u32 pberr; /* port 0/1 BIST error */ 119 u32 cmds; /* port 0/1 CMD status error */ 120 }; 121 122 #ifdef CONFIG_FSL_LSCH3 123 void fsl_lsch3_early_init_f(void); 124 int get_core_volt_from_fuse(void); 125 #elif defined(CONFIG_FSL_LSCH2) 126 void fsl_lsch2_early_init_f(void); 127 int setup_chip_volt(void); 128 /* Setup core vdd in unit mV */ 129 int board_setup_core_volt(u32 vdd); 130 #ifdef CONFIG_FSL_PFE 131 void init_pfe_scfg_dcfg_regs(void); 132 #endif 133 #endif 134 135 void cpu_name(char *name); 136 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 137 void erratum_a009635(void); 138 #endif 139 140 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 141 void erratum_a010315(void); 142 #endif 143 144 bool soc_has_dp_ddr(void); 145 bool soc_has_aiop(void); 146 #endif 147 148 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ 149