1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_NS_ACCESS_H_ 8 #define __FSL_NS_ACCESS_H_ 9 10 enum csu_cslx_ind { 11 CSU_CSLX_PCIE2_IO = 0, 12 CSU_CSLX_PCIE1_IO, 13 CSU_CSLX_MG2TPR_IP, 14 CSU_CSLX_IFC_MEM, 15 CSU_CSLX_OCRAM, 16 CSU_CSLX_GIC, 17 CSU_CSLX_PCIE1, 18 CSU_CSLX_OCRAM2, 19 CSU_CSLX_QSPI_MEM, 20 CSU_CSLX_PCIE2, 21 CSU_CSLX_SATA, 22 CSU_CSLX_USB1, 23 CSU_CSLX_QM_BM_SWPORTAL, 24 CSU_CSLX_PCIE3 = 16, 25 CSU_CSLX_PCIE3_IO, 26 CSU_CSLX_USB3 = 20, 27 CSU_CSLX_USB2, 28 CSU_CSLX_SERDES = 32, 29 CSU_CSLX_QDMA, 30 CSU_CSLX_LPUART2, 31 CSU_CSLX_LPUART1, 32 CSU_CSLX_LPUART4, 33 CSU_CSLX_LPUART3, 34 CSU_CSLX_LPUART6, 35 CSU_CSLX_LPUART5, 36 CSU_CSLX_DSPI1 = 41, 37 CSU_CSLX_QSPI, 38 CSU_CSLX_ESDHC, 39 CSU_CSLX_IFC = 45, 40 CSU_CSLX_I2C1, 41 CSU_CSLX_I2C3 = 48, 42 CSU_CSLX_I2C2, 43 CSU_CSLX_DUART2 = 50, 44 CSU_CSLX_DUART1, 45 CSU_CSLX_WDT2, 46 CSU_CSLX_WDT1, 47 CSU_CSLX_EDMA, 48 CSU_CSLX_SYS_CNT, 49 CSU_CSLX_DMA_MUX2, 50 CSU_CSLX_DMA_MUX1, 51 CSU_CSLX_DDR, 52 CSU_CSLX_QUICC, 53 CSU_CSLX_DCFG_CCU_RCPM = 60, 54 CSU_CSLX_SECURE_BOOTROM, 55 CSU_CSLX_SFP, 56 CSU_CSLX_TMU, 57 CSU_CSLX_SECURE_MONITOR, 58 CSU_CSLX_SCFG, 59 CSU_CSLX_FM = 66, 60 CSU_CSLX_SEC5_5, 61 CSU_CSLX_BM, 62 CSU_CSLX_QM, 63 CSU_CSLX_GPIO2 = 70, 64 CSU_CSLX_GPIO1, 65 CSU_CSLX_GPIO4, 66 CSU_CSLX_GPIO3, 67 CSU_CSLX_PLATFORM_CONT, 68 CSU_CSLX_CSU, 69 CSU_CSLX_IIC4 = 77, 70 CSU_CSLX_WDT4, 71 CSU_CSLX_WDT3, 72 CSU_CSLX_WDT5 = 81, 73 CSU_CSLX_FTM2 = 86, 74 CSU_CSLX_FTM1, 75 CSU_CSLX_FTM4, 76 CSU_CSLX_FTM3, 77 CSU_CSLX_FTM6 = 90, 78 CSU_CSLX_FTM5, 79 CSU_CSLX_FTM8, 80 CSU_CSLX_FTM7, 81 CSU_CSLX_DSCR = 121, 82 }; 83 84 static struct csu_ns_dev ns_dev[] = { 85 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, 86 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, 87 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, 88 {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, 89 {CSU_CSLX_OCRAM, CSU_ALL_RW}, 90 {CSU_CSLX_GIC, CSU_ALL_RW}, 91 {CSU_CSLX_PCIE1, CSU_ALL_RW}, 92 {CSU_CSLX_OCRAM2, CSU_ALL_RW}, 93 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, 94 {CSU_CSLX_PCIE2, CSU_ALL_RW}, 95 {CSU_CSLX_SATA, CSU_ALL_RW}, 96 {CSU_CSLX_USB1, CSU_ALL_RW}, 97 {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, 98 {CSU_CSLX_PCIE3, CSU_ALL_RW}, 99 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, 100 {CSU_CSLX_USB3, CSU_ALL_RW}, 101 {CSU_CSLX_USB2, CSU_ALL_RW}, 102 {CSU_CSLX_SERDES, CSU_ALL_RW}, 103 {CSU_CSLX_QDMA, CSU_ALL_RW}, 104 {CSU_CSLX_LPUART2, CSU_ALL_RW}, 105 {CSU_CSLX_LPUART1, CSU_ALL_RW}, 106 {CSU_CSLX_LPUART4, CSU_ALL_RW}, 107 {CSU_CSLX_LPUART3, CSU_ALL_RW}, 108 {CSU_CSLX_LPUART6, CSU_ALL_RW}, 109 {CSU_CSLX_LPUART5, CSU_ALL_RW}, 110 {CSU_CSLX_DSPI1, CSU_ALL_RW}, 111 {CSU_CSLX_QSPI, CSU_ALL_RW}, 112 {CSU_CSLX_ESDHC, CSU_ALL_RW}, 113 {CSU_CSLX_IFC, CSU_ALL_RW}, 114 {CSU_CSLX_I2C1, CSU_ALL_RW}, 115 {CSU_CSLX_I2C3, CSU_ALL_RW}, 116 {CSU_CSLX_I2C2, CSU_ALL_RW}, 117 {CSU_CSLX_DUART2, CSU_ALL_RW}, 118 {CSU_CSLX_DUART1, CSU_ALL_RW}, 119 {CSU_CSLX_WDT2, CSU_ALL_RW}, 120 {CSU_CSLX_WDT1, CSU_ALL_RW}, 121 {CSU_CSLX_EDMA, CSU_ALL_RW}, 122 {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, 123 {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, 124 {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, 125 {CSU_CSLX_DDR, CSU_ALL_RW}, 126 {CSU_CSLX_QUICC, CSU_ALL_RW}, 127 {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, 128 {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, 129 {CSU_CSLX_SFP, CSU_ALL_RW}, 130 {CSU_CSLX_TMU, CSU_ALL_RW}, 131 {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, 132 {CSU_CSLX_SCFG, CSU_ALL_RW}, 133 {CSU_CSLX_FM, CSU_ALL_RW}, 134 {CSU_CSLX_SEC5_5, CSU_ALL_RW}, 135 {CSU_CSLX_BM, CSU_ALL_RW}, 136 {CSU_CSLX_QM, CSU_ALL_RW}, 137 {CSU_CSLX_GPIO2, CSU_ALL_RW}, 138 {CSU_CSLX_GPIO1, CSU_ALL_RW}, 139 {CSU_CSLX_GPIO4, CSU_ALL_RW}, 140 {CSU_CSLX_GPIO3, CSU_ALL_RW}, 141 {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, 142 {CSU_CSLX_CSU, CSU_ALL_RW}, 143 {CSU_CSLX_IIC4, CSU_ALL_RW}, 144 {CSU_CSLX_WDT4, CSU_ALL_RW}, 145 {CSU_CSLX_WDT3, CSU_ALL_RW}, 146 {CSU_CSLX_WDT5, CSU_ALL_RW}, 147 {CSU_CSLX_FTM2, CSU_ALL_RW}, 148 {CSU_CSLX_FTM1, CSU_ALL_RW}, 149 {CSU_CSLX_FTM4, CSU_ALL_RW}, 150 {CSU_CSLX_FTM3, CSU_ALL_RW}, 151 {CSU_CSLX_FTM6, CSU_ALL_RW}, 152 {CSU_CSLX_FTM5, CSU_ALL_RW}, 153 {CSU_CSLX_FTM8, CSU_ALL_RW}, 154 {CSU_CSLX_FTM7, CSU_ALL_RW}, 155 {CSU_CSLX_DSCR, CSU_ALL_RW}, 156 }; 157 158 #endif 159