1 /* 2 * Copyright 2014-2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _FSL_LAYERSCAPE_MP_H 8 #define _FSL_LAYERSCAPE_MP_H 9 10 /* 11 * Each spin table element is defined as 12 * struct { 13 * uint64_t entry_addr; 14 * uint64_t status; 15 * uint64_t lpid; 16 * uint64_t os_arch; 17 * }; 18 * we pad this struct to 64 bytes so each entry is in its own cacheline 19 * the actual spin table is an array of these structures 20 */ 21 #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 22 #define SPIN_TABLE_ELEM_STATUS_IDX 1 23 #define SPIN_TABLE_ELEM_LPID_IDX 2 24 #define SPIN_TABLE_ELEM_OS_ARCH_IDX 3 25 #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ 26 #define SPIN_TABLE_ELEM_SIZE 64 27 28 #define id_to_core(x) ((x & 3) | (x >> 6)) 29 #ifndef __ASSEMBLY__ 30 extern u64 __spin_table[]; 31 extern u64 __real_cntfrq; 32 extern u64 *secondary_boot_code; 33 extern size_t __secondary_boot_code_size; 34 #ifdef CONFIG_MP 35 int fsl_layerscape_wake_seconday_cores(void); 36 #else 37 static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } 38 #endif 39 void *get_spin_tbl_addr(void); 40 phys_addr_t determine_mp_bootpg(void); 41 void secondary_boot_func(void); 42 int is_core_online(u64 cpu_id); 43 u32 cpu_pos_mask(void); 44 #endif 45 46 #define IH_ARCH_ARM 2 /* ARM */ 47 #define IH_ARCH_ARM64 22 /* ARM64 */ 48 49 #endif /* _FSL_LAYERSCAPE_MP_H */ 50