1 /* 2 * Copyright 2014-2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _FSL_LAYERSCAPE_MP_H 8 #define _FSL_LAYERSCAPE_MP_H 9 10 /* 11 * Each spin table element is defined as 12 * struct { 13 * uint64_t entry_addr; 14 * uint64_t status; 15 * uint64_t lpid; 16 * uint64_t arch_comp; 17 * }; 18 * we pad this struct to 64 bytes so each entry is in its own cacheline 19 * the actual spin table is an array of these structures 20 */ 21 #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 22 #define SPIN_TABLE_ELEM_STATUS_IDX 1 23 #define SPIN_TABLE_ELEM_LPID_IDX 2 24 /* compare os arch and cpu arch */ 25 #define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3 26 #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ 27 #define SPIN_TABLE_ELEM_SIZE 64 28 29 /* os arch is same as cpu arch */ 30 #define OS_ARCH_SAME 0 31 /* os arch is different from cpu arch */ 32 #define OS_ARCH_DIFF 1 33 34 #define id_to_core(x) ((x & 3) | (x >> 6)) 35 #ifndef __ASSEMBLY__ 36 extern u64 __spin_table[]; 37 extern u64 __real_cntfrq; 38 extern u64 *secondary_boot_code; 39 extern size_t __secondary_boot_code_size; 40 #ifdef CONFIG_MP 41 int fsl_layerscape_wake_seconday_cores(void); 42 #else 43 static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } 44 #endif 45 void *get_spin_tbl_addr(void); 46 phys_addr_t determine_mp_bootpg(void); 47 void secondary_boot_func(void); 48 int is_core_online(u64 cpu_id); 49 u32 cpu_pos_mask(void); 50 #endif 51 52 #endif /* _FSL_LAYERSCAPE_MP_H */ 53