1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014-2015, Freescale Semiconductor
4  */
5 
6 #ifndef _FSL_LAYERSCAPE_MP_H
7 #define _FSL_LAYERSCAPE_MP_H
8 
9 /*
10 * Each spin table element is defined as
11 * struct {
12 *      uint64_t entry_addr;
13 *      uint64_t status;
14 *      uint64_t lpid;
15 *      uint64_t arch_comp;
16 * };
17 * we pad this struct to 64 bytes so each entry is in its own cacheline
18 * the actual spin table is an array of these structures
19 */
20 #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX	0
21 #define SPIN_TABLE_ELEM_STATUS_IDX	1
22 #define SPIN_TABLE_ELEM_LPID_IDX	2
23 /* compare os arch and cpu arch */
24 #define SPIN_TABLE_ELEM_ARCH_COMP_IDX	3
25 #define WORDS_PER_SPIN_TABLE_ENTRY	8	/* pad to 64 bytes */
26 #define SPIN_TABLE_ELEM_SIZE		64
27 
28 /* os arch is same as cpu arch */
29 #define OS_ARCH_SAME			0
30 /* os arch is different from cpu arch */
31 #define OS_ARCH_DIFF			1
32 
33 #define id_to_core(x)	((x & 3) | (x >> 6))
34 #ifndef __ASSEMBLY__
35 extern u64 __spin_table[];
36 extern u64 __real_cntfrq;
37 extern u64 *secondary_boot_code;
38 extern size_t __secondary_boot_code_size;
39 #ifdef CONFIG_MP
40 int fsl_layerscape_wake_seconday_cores(void);
41 #else
42 static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
43 #endif
44 void *get_spin_tbl_addr(void);
45 phys_addr_t determine_mp_bootpg(void);
46 void secondary_boot_func(void);
47 int is_core_online(u64 cpu_id);
48 u32 cpu_pos_mask(void);
49 #endif
50 
51 #endif /* _FSL_LAYERSCAPE_MP_H */
52