1 /* 2 * LayerScape Internal Memory Map 3 * 4 * Copyright 2014 Freescale Semiconductor, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_ 10 #define __ARCH_FSL_LSCH3_IMMAP_H_ 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) 15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) 17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) 18 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) 19 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) 20 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) 21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) 22 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) 23 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) 24 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) 25 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) 26 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) 27 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 28 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 29 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 30 0x18A0) 31 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) 32 #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) 33 34 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) 35 #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) 36 #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) 37 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) 38 39 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL 40 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL 41 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL 42 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL 43 44 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) 45 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) 46 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) 47 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) 48 49 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 50 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) 51 52 /* TZ Address Space Controller Definitions */ 53 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 54 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 55 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 56 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 57 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 58 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 59 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 60 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 61 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 62 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 63 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 64 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 65 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 66 67 /* SATA */ 68 #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) 69 #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) 70 71 /* SFP */ 72 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 73 74 /* SEC */ 75 #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull 76 #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull 77 #define CONFIG_SYS_FSL_SEC_ADDR \ 78 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 79 #define CONFIG_SYS_FSL_JR0_ADDR \ 80 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 81 82 /* Security Monitor */ 83 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 84 85 /* MMU 500 */ 86 #define SMMU_SCR0 (SMMU_BASE + 0x0) 87 #define SMMU_SCR1 (SMMU_BASE + 0x4) 88 #define SMMU_SCR2 (SMMU_BASE + 0x8) 89 #define SMMU_SACR (SMMU_BASE + 0x10) 90 #define SMMU_IDR0 (SMMU_BASE + 0x20) 91 #define SMMU_IDR1 (SMMU_BASE + 0x24) 92 93 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 94 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 95 #define SMMU_NSACR (SMMU_BASE + 0x410) 96 97 #define SCR0_CLIENTPD_MASK 0x00000001 98 #define SCR0_USFCFG_MASK 0x00000400 99 100 101 /* PCIe */ 102 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 103 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 104 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 105 #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) 106 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL 107 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL 108 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL 109 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL 110 /* LUT registers */ 111 #define PCIE_LUT_BASE 0x80000 112 #define PCIE_LUT_LCTRL0 0x7F8 113 #define PCIE_LUT_DBG 0x7FC 114 #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) 115 #define PCIE_LUT_LDR(n) (0x804 + (n) * 8) 116 #define PCIE_LUT_ENABLE (1 << 31) 117 #define PCIE_LUT_ENTRY_COUNT 32 118 119 /* Device Configuration */ 120 #define DCFG_BASE 0x01e00000 121 #define DCFG_PORSR1 0x000 122 #define DCFG_PORSR1_RCW_SRC 0xff800000 123 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 124 #define DCFG_RCWSR13 0x130 125 #define DCFG_RCWSR13_DSPI (0 << 8) 126 #define DCFG_RCWSR15 0x138 127 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3 128 129 #define DCFG_DCSR_BASE 0X700100000ULL 130 #define DCFG_DCSR_PORCR1 0x000 131 132 /* Interrupt Sampling Control */ 133 #define ISC_BASE 0x01F70000 134 #define IRQCR_OFFSET 0x14 135 136 /* Supplemental Configuration */ 137 #define SCFG_BASE 0x01fc0000 138 #define SCFG_USB3PRM1CR 0x000 139 #define SCFG_USB3PRM1CR_INIT 0x27672b2a 140 #define SCFG_QSPICLKCTLR 0x10 141 142 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 143 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 144 #define TP_ITYP_TYPE_ARM 0x0 145 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 146 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 147 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 148 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 149 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 150 #define TY_ITYP_VER_A7 0x1 151 #define TY_ITYP_VER_A53 0x2 152 #define TY_ITYP_VER_A57 0x3 153 #define TY_ITYP_VER_A72 0x4 154 155 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 156 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 157 #define TP_INIT_PER_CLUSTER 4 158 /* This is chassis generation 3 */ 159 #ifndef __ASSEMBLY__ 160 struct sys_info { 161 unsigned long freq_processor[CONFIG_MAX_CPUS]; 162 unsigned long freq_systembus; 163 unsigned long freq_ddrbus; 164 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 165 unsigned long freq_ddrbus2; 166 #endif 167 unsigned long freq_localbus; 168 unsigned long freq_qe; 169 #ifdef CONFIG_SYS_DPAA_FMAN 170 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 171 #endif 172 #ifdef CONFIG_SYS_DPAA_QBMAN 173 unsigned long freq_qman; 174 #endif 175 #ifdef CONFIG_SYS_DPAA_PME 176 unsigned long freq_pme; 177 #endif 178 }; 179 180 /* Global Utilities Block */ 181 struct ccsr_gur { 182 u32 porsr1; /* POR status 1 */ 183 u32 porsr2; /* POR status 2 */ 184 u8 res_008[0x20-0x8]; 185 u32 gpporcr1; /* General-purpose POR configuration */ 186 u32 gpporcr2; /* General-purpose POR configuration 2 */ 187 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 188 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F 189 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 190 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F 191 u32 dcfg_fusesr; /* Fuse status register */ 192 u32 gpporcr3; 193 u32 gpporcr4; 194 u8 res_034[0x70-0x34]; 195 u32 devdisr; /* Device disable control */ 196 u32 devdisr2; /* Device disable control 2 */ 197 u32 devdisr3; /* Device disable control 3 */ 198 u32 devdisr4; /* Device disable control 4 */ 199 u32 devdisr5; /* Device disable control 5 */ 200 u32 devdisr6; /* Device disable control 6 */ 201 u32 devdisr7; /* Device disable control 7 */ 202 #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 203 #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 204 #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 205 #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 206 #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 207 #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 208 #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 209 #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 210 #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 211 #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 212 #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 213 #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 214 #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 215 #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 216 #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 217 #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 218 #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 219 #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 220 #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 221 #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 222 #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 223 #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 224 #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 225 #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 226 u8 res_08c[0x90-0x8c]; 227 u32 coredisru; /* uppper portion for support of 64 cores */ 228 u32 coredisrl; /* lower portion for support of 64 cores */ 229 u8 res_098[0xa0-0x98]; 230 u32 pvr; /* Processor version */ 231 u32 svr; /* System version */ 232 u32 mvr; /* Manufacturing version */ 233 u8 res_0ac[0x100-0xac]; 234 u32 rcwsr[32]; /* Reset control word status */ 235 236 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 237 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f 238 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 239 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f 240 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 241 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f 242 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 243 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 244 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 245 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 246 #define RCW_SB_EN_REG_INDEX 9 247 #define RCW_SB_EN_MASK 0x00000400 248 249 u8 res_180[0x200-0x180]; 250 u32 scratchrw[32]; /* Scratch Read/Write */ 251 u8 res_280[0x300-0x280]; 252 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 253 u8 res_310[0x400-0x310]; 254 u32 bootlocptrl; /* Boot location pointer low-order addr */ 255 u32 bootlocptrh; /* Boot location pointer high-order addr */ 256 u8 res_408[0x500-0x408]; 257 u8 res_500[0x740-0x500]; /* add more registers when needed */ 258 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 259 struct { 260 u32 upper; 261 u32 lower; 262 } tp_cluster[3]; /* Core Cluster n Topology Register */ 263 u8 res_858[0x1000-0x858]; 264 }; 265 266 267 struct ccsr_clk_cluster_group { 268 struct { 269 u8 res_00[0x10]; 270 u32 csr; 271 u8 res_14[0x20-0x14]; 272 } hwncsr[3]; 273 u8 res_60[0x80-0x60]; 274 struct { 275 u32 gsr; 276 u8 res_84[0xa0-0x84]; 277 } pllngsr[3]; 278 u8 res_e0[0x100-0xe0]; 279 }; 280 281 struct ccsr_clk_ctrl { 282 struct { 283 u32 csr; /* core cluster n clock control status */ 284 u8 res_04[0x20-0x04]; 285 } clkcncsr[8]; 286 }; 287 288 struct ccsr_reset { 289 u32 rstcr; /* 0x000 */ 290 u32 rstcrsp; /* 0x004 */ 291 u8 res_008[0x10-0x08]; /* 0x008 */ 292 u32 rstrqmr1; /* 0x010 */ 293 u32 rstrqmr2; /* 0x014 */ 294 u32 rstrqsr1; /* 0x018 */ 295 u32 rstrqsr2; /* 0x01c */ 296 u32 rstrqwdtmrl; /* 0x020 */ 297 u32 rstrqwdtmru; /* 0x024 */ 298 u8 res_028[0x30-0x28]; /* 0x028 */ 299 u32 rstrqwdtsrl; /* 0x030 */ 300 u32 rstrqwdtsru; /* 0x034 */ 301 u8 res_038[0x60-0x38]; /* 0x038 */ 302 u32 brrl; /* 0x060 */ 303 u32 brru; /* 0x064 */ 304 u8 res_068[0x80-0x68]; /* 0x068 */ 305 u32 pirset; /* 0x080 */ 306 u32 pirclr; /* 0x084 */ 307 u8 res_088[0x90-0x88]; /* 0x088 */ 308 u32 brcorenbr; /* 0x090 */ 309 u8 res_094[0x100-0x94]; /* 0x094 */ 310 u32 rcw_reqr; /* 0x100 */ 311 u32 rcw_completion; /* 0x104 */ 312 u8 res_108[0x110-0x108]; /* 0x108 */ 313 u32 pbi_reqr; /* 0x110 */ 314 u32 pbi_completion; /* 0x114 */ 315 u8 res_118[0xa00-0x118]; /* 0x118 */ 316 u32 qmbm_warmrst; /* 0xa00 */ 317 u32 soc_warmrst; /* 0xa04 */ 318 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ 319 u32 ip_rev1; /* 0xbf8 */ 320 u32 ip_rev2; /* 0xbfc */ 321 }; 322 323 #endif /*__ASSEMBLY__*/ 324 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ 325