1 /*
2  * LayerScape Internal Memory Map
3  *
4  * Copyright 2014 Freescale Semiconductor, Inc.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
10 #define __ARCH_FSL_LSCH3_IMMAP_H_
11 
12 #define CONFIG_SYS_IMMR				0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
18 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
19 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
20 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
22 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
23 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
24 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
25 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
26 #define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
27 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
28 						 0x18A0)
29 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
30 
31 #define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
32 #define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
33 #define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
34 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
35 
36 /* SP (Cortex-A5) related */
37 #define CONFIG_SYS_FSL_SP_ADDR			(CONFIG_SYS_IMMR + 0x00F00000)
38 #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR		(CONFIG_SYS_FSL_SP_ADDR)
39 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1		(CONFIG_SYS_FSL_SP_ADDR)
40 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2		\
41 					(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
42 #define CONFIG_SYS_FSL_SP_LOOPBACK_DUART	\
43 					(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
44 
45 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
46 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
47 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
48 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR		0x700133000ULL
49 
50 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
51 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
52 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
53 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
54 
55 #define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
56 #define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
57 
58 /* TZ Address Space Controller Definitions */
59 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
60 #define TZASC2_BASE			0x01110000	/* as per CCSR map. */
61 #define TZASC3_BASE			0x01120000	/* as per CCSR map. */
62 #define TZASC4_BASE			0x01130000	/* as per CCSR map. */
63 #define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
64 #define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
65 #define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
66 #define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
67 #define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
68 #define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
69 #define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
70 #define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
71 #define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
72 
73 /* SATA */
74 #define AHCI_BASE_ADDR1				(CONFIG_SYS_IMMR + 0x02200000)
75 #define AHCI_BASE_ADDR2				(CONFIG_SYS_IMMR + 0x02210000)
76 
77 /* SFP */
78 #define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
79 
80 /* SEC */
81 #define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
82 #define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
83 #define CONFIG_SYS_FSL_SEC_ADDR \
84 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
85 #define CONFIG_SYS_FSL_JR0_ADDR \
86 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
87 
88 /* Security Monitor */
89 #define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
90 
91 /* MMU 500 */
92 #define SMMU_SCR0			(SMMU_BASE + 0x0)
93 #define SMMU_SCR1			(SMMU_BASE + 0x4)
94 #define SMMU_SCR2			(SMMU_BASE + 0x8)
95 #define SMMU_SACR			(SMMU_BASE + 0x10)
96 #define SMMU_IDR0			(SMMU_BASE + 0x20)
97 #define SMMU_IDR1			(SMMU_BASE + 0x24)
98 
99 #define SMMU_NSCR0			(SMMU_BASE + 0x400)
100 #define SMMU_NSCR2			(SMMU_BASE + 0x408)
101 #define SMMU_NSACR			(SMMU_BASE + 0x410)
102 
103 #define SCR0_CLIENTPD_MASK		0x00000001
104 #define SCR0_USFCFG_MASK		0x00000400
105 
106 
107 /* PCIe */
108 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
109 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
110 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
111 #define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
112 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
113 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
114 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
115 #define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
116 /* LUT registers */
117 #define PCIE_LUT_BASE				0x80000
118 #define PCIE_LUT_LCTRL0				0x7F8
119 #define PCIE_LUT_DBG				0x7FC
120 #define PCIE_LUT_UDR(n)         (0x800 + (n) * 8)
121 #define PCIE_LUT_LDR(n)         (0x804 + (n) * 8)
122 #define PCIE_LUT_ENABLE         (1 << 31)
123 #define PCIE_LUT_ENTRY_COUNT    32
124 
125 /* Device Configuration */
126 #define DCFG_BASE		0x01e00000
127 #define DCFG_PORSR1			0x000
128 #define DCFG_PORSR1_RCW_SRC		0xff800000
129 #define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
130 #define DCFG_RCWSR13			0x130
131 #define DCFG_RCWSR13_DSPI		(0 << 8)
132 #define DCFG_RCWSR15			0x138
133 #define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
134 
135 #define DCFG_DCSR_BASE		0X700100000ULL
136 #define DCFG_DCSR_PORCR1		0x000
137 
138 /* Interrupt Sampling Control */
139 #define ISC_BASE		0x01F70000
140 #define IRQCR_OFFSET		0x14
141 
142 /* Supplemental Configuration */
143 #define SCFG_BASE		0x01fc0000
144 #define SCFG_USB3PRM1CR			0x000
145 #define SCFG_USB3PRM1CR_INIT		0x27672b2a
146 #define SCFG_QSPICLKCTLR	0x10
147 
148 #define TP_ITYP_AV		0x00000001	/* Initiator available */
149 #define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
150 #define TP_ITYP_TYPE_ARM	0x0
151 #define TP_ITYP_TYPE_PPC	0x1		/* PowerPC */
152 #define TP_ITYP_TYPE_OTHER	0x2		/* StarCore DSP */
153 #define TP_ITYP_TYPE_HA		0x3		/* HW Accelerator */
154 #define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
155 #define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
156 #define TY_ITYP_VER_A7		0x1
157 #define TY_ITYP_VER_A53		0x2
158 #define TY_ITYP_VER_A57		0x3
159 #define TY_ITYP_VER_A72		0x4
160 
161 #define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
162 #define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
163 #define TP_INIT_PER_CLUSTER     4
164 /* This is chassis generation 3 */
165 
166 struct sys_info {
167 	unsigned long freq_processor[CONFIG_MAX_CPUS];
168 	unsigned long freq_systembus;
169 	unsigned long freq_ddrbus;
170 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
171 	unsigned long freq_ddrbus2;
172 #endif
173 	unsigned long freq_localbus;
174 	unsigned long freq_qe;
175 #ifdef CONFIG_SYS_DPAA_FMAN
176 	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
177 #endif
178 #ifdef CONFIG_SYS_DPAA_QBMAN
179 	unsigned long freq_qman;
180 #endif
181 #ifdef CONFIG_SYS_DPAA_PME
182 	unsigned long freq_pme;
183 #endif
184 };
185 
186 /* Global Utilities Block */
187 struct ccsr_gur {
188 	u32	porsr1;		/* POR status 1 */
189 	u32	porsr2;		/* POR status 2 */
190 	u8	res_008[0x20-0x8];
191 	u32	gpporcr1;	/* General-purpose POR configuration */
192 	u32	gpporcr2;	/* General-purpose POR configuration 2 */
193 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT	25
194 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK	0x1F
195 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT	20
196 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK	0x1F
197 	u32	dcfg_fusesr;	/* Fuse status register */
198 	u32	gpporcr3;
199 	u32	gpporcr4;
200 	u8	res_034[0x70-0x34];
201 	u32	devdisr;	/* Device disable control */
202 	u32	devdisr2;	/* Device disable control 2 */
203 	u32	devdisr3;	/* Device disable control 3 */
204 	u32	devdisr4;	/* Device disable control 4 */
205 	u32	devdisr5;	/* Device disable control 5 */
206 	u32	devdisr6;	/* Device disable control 6 */
207 	u32	devdisr7;	/* Device disable control 7 */
208 #define FSL_CHASSIS3_DEVDISR2_DPMAC1	0x00000001
209 #define FSL_CHASSIS3_DEVDISR2_DPMAC2	0x00000002
210 #define FSL_CHASSIS3_DEVDISR2_DPMAC3	0x00000004
211 #define FSL_CHASSIS3_DEVDISR2_DPMAC4	0x00000008
212 #define FSL_CHASSIS3_DEVDISR2_DPMAC5	0x00000010
213 #define FSL_CHASSIS3_DEVDISR2_DPMAC6	0x00000020
214 #define FSL_CHASSIS3_DEVDISR2_DPMAC7	0x00000040
215 #define FSL_CHASSIS3_DEVDISR2_DPMAC8	0x00000080
216 #define FSL_CHASSIS3_DEVDISR2_DPMAC9	0x00000100
217 #define FSL_CHASSIS3_DEVDISR2_DPMAC10	0x00000200
218 #define FSL_CHASSIS3_DEVDISR2_DPMAC11	0x00000400
219 #define FSL_CHASSIS3_DEVDISR2_DPMAC12	0x00000800
220 #define FSL_CHASSIS3_DEVDISR2_DPMAC13	0x00001000
221 #define FSL_CHASSIS3_DEVDISR2_DPMAC14	0x00002000
222 #define FSL_CHASSIS3_DEVDISR2_DPMAC15	0x00004000
223 #define FSL_CHASSIS3_DEVDISR2_DPMAC16	0x00008000
224 #define FSL_CHASSIS3_DEVDISR2_DPMAC17	0x00010000
225 #define FSL_CHASSIS3_DEVDISR2_DPMAC18	0x00020000
226 #define FSL_CHASSIS3_DEVDISR2_DPMAC19	0x00040000
227 #define FSL_CHASSIS3_DEVDISR2_DPMAC20	0x00080000
228 #define FSL_CHASSIS3_DEVDISR2_DPMAC21	0x00100000
229 #define FSL_CHASSIS3_DEVDISR2_DPMAC22	0x00200000
230 #define FSL_CHASSIS3_DEVDISR2_DPMAC23	0x00400000
231 #define FSL_CHASSIS3_DEVDISR2_DPMAC24	0x00800000
232 	u8	res_08c[0x90-0x8c];
233 	u32	coredisru;	/* uppper portion for support of 64 cores */
234 	u32	coredisrl;	/* lower portion for support of 64 cores */
235 	u8	res_098[0xa0-0x98];
236 	u32	pvr;		/* Processor version */
237 	u32	svr;		/* System version */
238 	u32	mvr;		/* Manufacturing version */
239 	u8	res_0ac[0x100-0xac];
240 	u32	rcwsr[32];	/* Reset control word status */
241 
242 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT	2
243 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK	0x1f
244 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT	10
245 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
246 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT	18
247 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK	0x3f
248 #define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK	0x00FF0000
249 #define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT	16
250 #define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK	0xFF000000
251 #define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT	24
252 #define RCW_SB_EN_REG_INDEX	9
253 #define RCW_SB_EN_MASK		0x00000400
254 
255 	u8	res_180[0x200-0x180];
256 	u32	scratchrw[32];	/* Scratch Read/Write */
257 	u8	res_280[0x300-0x280];
258 	u32	scratchw1r[4];	/* Scratch Read (Write once) */
259 	u8	res_310[0x400-0x310];
260 	u32	bootlocptrl;	/* Boot location pointer low-order addr */
261 	u32	bootlocptrh;	/* Boot location pointer high-order addr */
262 	u8	res_408[0x500-0x408];
263 	u8	res_500[0x740-0x500];	/* add more registers when needed */
264 	u32	tp_ityp[64];	/* Topology Initiator Type Register */
265 	struct {
266 		u32	upper;
267 		u32	lower;
268 	} tp_cluster[3];	/* Core Cluster n Topology Register */
269 	u8	res_858[0x1000-0x858];
270 };
271 
272 
273 struct ccsr_clk_cluster_group {
274 	struct {
275 		u8	res_00[0x10];
276 		u32	csr;
277 		u8	res_14[0x20-0x14];
278 	} hwncsr[3];
279 	u8	res_60[0x80-0x60];
280 	struct {
281 		u32	gsr;
282 		u8	res_84[0xa0-0x84];
283 	} pllngsr[3];
284 	u8	res_e0[0x100-0xe0];
285 };
286 
287 struct ccsr_clk_ctrl {
288 	struct {
289 		u32 csr;	/* core cluster n clock control status */
290 		u8  res_04[0x20-0x04];
291 	} clkcncsr[8];
292 };
293 
294 struct ccsr_reset {
295 	u32 rstcr;			/* 0x000 */
296 	u32 rstcrsp;			/* 0x004 */
297 	u8 res_008[0x10-0x08];		/* 0x008 */
298 	u32 rstrqmr1;			/* 0x010 */
299 	u32 rstrqmr2;			/* 0x014 */
300 	u32 rstrqsr1;			/* 0x018 */
301 	u32 rstrqsr2;			/* 0x01c */
302 	u32 rstrqwdtmrl;		/* 0x020 */
303 	u32 rstrqwdtmru;		/* 0x024 */
304 	u8 res_028[0x30-0x28];		/* 0x028 */
305 	u32 rstrqwdtsrl;		/* 0x030 */
306 	u32 rstrqwdtsru;		/* 0x034 */
307 	u8 res_038[0x60-0x38];		/* 0x038 */
308 	u32 brrl;			/* 0x060 */
309 	u32 brru;			/* 0x064 */
310 	u8 res_068[0x80-0x68];		/* 0x068 */
311 	u32 pirset;			/* 0x080 */
312 	u32 pirclr;			/* 0x084 */
313 	u8 res_088[0x90-0x88];		/* 0x088 */
314 	u32 brcorenbr;			/* 0x090 */
315 	u8 res_094[0x100-0x94];		/* 0x094 */
316 	u32 rcw_reqr;			/* 0x100 */
317 	u32 rcw_completion;		/* 0x104 */
318 	u8 res_108[0x110-0x108];	/* 0x108 */
319 	u32 pbi_reqr;			/* 0x110 */
320 	u32 pbi_completion;		/* 0x114 */
321 	u8 res_118[0xa00-0x118];	/* 0x118 */
322 	u32 qmbm_warmrst;		/* 0xa00 */
323 	u32 soc_warmrst;		/* 0xa04 */
324 	u8 res_a08[0xbf8-0xa08];	/* 0xa08 */
325 	u32 ip_rev1;			/* 0xbf8 */
326 	u32 ip_rev2;			/* 0xbfc */
327 };
328 
329 uint get_svr(void);
330 
331 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
332