1 /*
2  * LayerScape Internal Memory Map
3  *
4  * Copyright 2014 Freescale Semiconductor, Inc.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
10 #define __ARCH_FSL_LSCH3_IMMAP_H_
11 
12 #define CONFIG_SYS_IMMR				0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
18 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
19 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
20 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
22 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
23 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
24 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
25 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
26 #define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
27 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
28 						 0x18A0)
29 
30 #define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
31 #define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
32 #define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
33 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
34 
35 /* SP (Cortex-A5) related */
36 #define CONFIG_SYS_FSL_SP_ADDR			(CONFIG_SYS_IMMR + 0x00F00000)
37 #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR		(CONFIG_SYS_FSL_SP_ADDR)
38 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1		(CONFIG_SYS_FSL_SP_ADDR)
39 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2		\
40 					(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
41 #define CONFIG_SYS_FSL_SP_LOOPBACK_DUART	\
42 					(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
43 
44 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
45 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
46 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
47 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR		0x700133000ULL
48 
49 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
50 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
51 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
52 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
53 
54 #define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
55 #define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02110000)
56 
57 /* TZ Address Space Controller Definitions */
58 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
59 #define TZASC2_BASE			0x01110000	/* as per CCSR map. */
60 #define TZASC3_BASE			0x01120000	/* as per CCSR map. */
61 #define TZASC4_BASE			0x01130000	/* as per CCSR map. */
62 #define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
63 #define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
64 #define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
65 #define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
66 #define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
67 #define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
68 #define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
69 #define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
70 #define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
71 
72 /* PCIe */
73 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
74 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
75 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
76 #define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
77 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
78 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
79 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
80 #define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
81 /* LUT registers */
82 #define PCIE_LUT_BASE				0x80000
83 #define PCIE_LUT_LCTRL0				0x7F8
84 #define PCIE_LUT_DBG				0x7FC
85 
86 /* Device Configuration */
87 #define DCFG_BASE		0x01e00000
88 #define DCFG_PORSR1			0x000
89 #define DCFG_PORSR1_RCW_SRC		0xff800000
90 #define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
91 #define DCFG_RCWSR13			0x130
92 #define DCFG_RCWSR13_DSPI		(0 << 8)
93 
94 #define DCFG_DCSR_BASE		0X700100000ULL
95 #define DCFG_DCSR_PORCR1		0x000
96 
97 /* Supplemental Configuration */
98 #define SCFG_BASE		0x01fc0000
99 #define SCFG_USB3PRM1CR			0x000
100 
101 #define TP_ITYP_AV		0x00000001	/* Initiator available */
102 #define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
103 #define TP_ITYP_TYPE_ARM	0x0
104 #define TP_ITYP_TYPE_PPC	0x1		/* PowerPC */
105 #define TP_ITYP_TYPE_OTHER	0x2		/* StarCore DSP */
106 #define TP_ITYP_TYPE_HA		0x3		/* HW Accelerator */
107 #define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
108 #define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
109 #define TY_ITYP_VER_A7		0x1
110 #define TY_ITYP_VER_A53		0x2
111 #define TY_ITYP_VER_A57		0x3
112 
113 #define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
114 #define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
115 #define TP_INIT_PER_CLUSTER     4
116 /* This is chassis generation 3 */
117 
118 struct sys_info {
119 	unsigned long freq_processor[CONFIG_MAX_CPUS];
120 	unsigned long freq_systembus;
121 	unsigned long freq_ddrbus;
122 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
123 	unsigned long freq_ddrbus2;
124 #endif
125 	unsigned long freq_localbus;
126 	unsigned long freq_qe;
127 #ifdef CONFIG_SYS_DPAA_FMAN
128 	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
129 #endif
130 #ifdef CONFIG_SYS_DPAA_QBMAN
131 	unsigned long freq_qman;
132 #endif
133 #ifdef CONFIG_SYS_DPAA_PME
134 	unsigned long freq_pme;
135 #endif
136 };
137 
138 /* Global Utilities Block */
139 struct ccsr_gur {
140 	u32	porsr1;		/* POR status 1 */
141 	u32	porsr2;		/* POR status 2 */
142 	u8	res_008[0x20-0x8];
143 	u32	gpporcr1;	/* General-purpose POR configuration */
144 	u32	gpporcr2;	/* General-purpose POR configuration 2 */
145 	u32	dcfg_fusesr;	/* Fuse status register */
146 	u32	gpporcr3;
147 	u32	gpporcr4;
148 	u8	res_034[0x70-0x34];
149 	u32	devdisr;	/* Device disable control */
150 	u32	devdisr2;	/* Device disable control 2 */
151 	u32	devdisr3;	/* Device disable control 3 */
152 	u32	devdisr4;	/* Device disable control 4 */
153 	u32	devdisr5;	/* Device disable control 5 */
154 	u32	devdisr6;	/* Device disable control 6 */
155 	u32	devdisr7;	/* Device disable control 7 */
156 #define FSL_CHASSIS3_DEVDISR2_DPMAC1	0x00000001
157 #define FSL_CHASSIS3_DEVDISR2_DPMAC2	0x00000002
158 #define FSL_CHASSIS3_DEVDISR2_DPMAC3	0x00000004
159 #define FSL_CHASSIS3_DEVDISR2_DPMAC4	0x00000008
160 #define FSL_CHASSIS3_DEVDISR2_DPMAC5	0x00000010
161 #define FSL_CHASSIS3_DEVDISR2_DPMAC6	0x00000020
162 #define FSL_CHASSIS3_DEVDISR2_DPMAC7	0x00000040
163 #define FSL_CHASSIS3_DEVDISR2_DPMAC8	0x00000080
164 #define FSL_CHASSIS3_DEVDISR2_DPMAC9	0x00000100
165 #define FSL_CHASSIS3_DEVDISR2_DPMAC10	0x00000200
166 #define FSL_CHASSIS3_DEVDISR2_DPMAC11	0x00000400
167 #define FSL_CHASSIS3_DEVDISR2_DPMAC12	0x00000800
168 #define FSL_CHASSIS3_DEVDISR2_DPMAC13	0x00001000
169 #define FSL_CHASSIS3_DEVDISR2_DPMAC14	0x00002000
170 #define FSL_CHASSIS3_DEVDISR2_DPMAC15	0x00004000
171 #define FSL_CHASSIS3_DEVDISR2_DPMAC16	0x00008000
172 #define FSL_CHASSIS3_DEVDISR2_DPMAC17	0x00010000
173 #define FSL_CHASSIS3_DEVDISR2_DPMAC18	0x00020000
174 #define FSL_CHASSIS3_DEVDISR2_DPMAC19	0x00040000
175 #define FSL_CHASSIS3_DEVDISR2_DPMAC20	0x00080000
176 #define FSL_CHASSIS3_DEVDISR2_DPMAC21	0x00100000
177 #define FSL_CHASSIS3_DEVDISR2_DPMAC22	0x00200000
178 #define FSL_CHASSIS3_DEVDISR2_DPMAC23	0x00400000
179 #define FSL_CHASSIS3_DEVDISR2_DPMAC24	0x00800000
180 	u8	res_08c[0x90-0x8c];
181 	u32	coredisru;	/* uppper portion for support of 64 cores */
182 	u32	coredisrl;	/* lower portion for support of 64 cores */
183 	u8	res_098[0xa0-0x98];
184 	u32	pvr;		/* Processor version */
185 	u32	svr;		/* System version */
186 	u32	mvr;		/* Manufacturing version */
187 	u8	res_0ac[0x100-0xac];
188 	u32	rcwsr[32];	/* Reset control word status */
189 
190 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT	2
191 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK	0x1f
192 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT	10
193 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
194 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT	18
195 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK	0x3f
196 #define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK	0x00FF0000
197 #define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT	16
198 #define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK	0xFF000000
199 #define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT	24
200 
201 	u8	res_180[0x200-0x180];
202 	u32	scratchrw[32];	/* Scratch Read/Write */
203 	u8	res_280[0x300-0x280];
204 	u32	scratchw1r[4];	/* Scratch Read (Write once) */
205 	u8	res_310[0x400-0x310];
206 	u32	bootlocptrl;	/* Boot location pointer low-order addr */
207 	u32	bootlocptrh;	/* Boot location pointer high-order addr */
208 	u8	res_408[0x500-0x408];
209 	u8	res_500[0x740-0x500];	/* add more registers when needed */
210 	u32	tp_ityp[64];	/* Topology Initiator Type Register */
211 	struct {
212 		u32	upper;
213 		u32	lower;
214 	} tp_cluster[3];	/* Core Cluster n Topology Register */
215 	u8	res_858[0x1000-0x858];
216 };
217 
218 
219 struct ccsr_clk_cluster_group {
220 	struct {
221 		u8	res_00[0x10];
222 		u32	csr;
223 		u8	res_14[0x20-0x14];
224 	} hwncsr[3];
225 	u8	res_60[0x80-0x60];
226 	struct {
227 		u32	gsr;
228 		u8	res_84[0xa0-0x84];
229 	} pllngsr[3];
230 	u8	res_e0[0x100-0xe0];
231 };
232 
233 struct ccsr_clk_ctrl {
234 	struct {
235 		u32 csr;	/* core cluster n clock control status */
236 		u8  res_04[0x20-0x04];
237 	} clkcncsr[8];
238 };
239 
240 struct ccsr_reset {
241 	u32 rstcr;			/* 0x000 */
242 	u32 rstcrsp;			/* 0x004 */
243 	u8 res_008[0x10-0x08];		/* 0x008 */
244 	u32 rstrqmr1;			/* 0x010 */
245 	u32 rstrqmr2;			/* 0x014 */
246 	u32 rstrqsr1;			/* 0x018 */
247 	u32 rstrqsr2;			/* 0x01c */
248 	u32 rstrqwdtmrl;		/* 0x020 */
249 	u32 rstrqwdtmru;		/* 0x024 */
250 	u8 res_028[0x30-0x28];		/* 0x028 */
251 	u32 rstrqwdtsrl;		/* 0x030 */
252 	u32 rstrqwdtsru;		/* 0x034 */
253 	u8 res_038[0x60-0x38];		/* 0x038 */
254 	u32 brrl;			/* 0x060 */
255 	u32 brru;			/* 0x064 */
256 	u8 res_068[0x80-0x68];		/* 0x068 */
257 	u32 pirset;			/* 0x080 */
258 	u32 pirclr;			/* 0x084 */
259 	u8 res_088[0x90-0x88];		/* 0x088 */
260 	u32 brcorenbr;			/* 0x090 */
261 	u8 res_094[0x100-0x94];		/* 0x094 */
262 	u32 rcw_reqr;			/* 0x100 */
263 	u32 rcw_completion;		/* 0x104 */
264 	u8 res_108[0x110-0x108];	/* 0x108 */
265 	u32 pbi_reqr;			/* 0x110 */
266 	u32 pbi_completion;		/* 0x114 */
267 	u8 res_118[0xa00-0x118];	/* 0x118 */
268 	u32 qmbm_warmrst;		/* 0xa00 */
269 	u32 soc_warmrst;		/* 0xa04 */
270 	u8 res_a08[0xbf8-0xa08];	/* 0xa08 */
271 	u32 ip_rev1;			/* 0xbf8 */
272 	u32 ip_rev2;			/* 0xbfc */
273 };
274 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
275