1 /* 2 * Copyright 2013-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 8 #define __ARCH_FSL_LSCH2_IMMAP_H__ 9 10 #include <fsl_immap.h> 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_DCSRBAR 0x20000000 14 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) 15 16 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 17 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) 18 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 19 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 20 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 21 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 22 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 23 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 24 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 25 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 26 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 27 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 28 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 29 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 30 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 31 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 32 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 33 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 34 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 35 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 36 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 37 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 38 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 39 #define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) 40 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) 41 #define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000) 42 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 43 44 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 45 46 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 47 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 48 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 49 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 50 51 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 52 53 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 54 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 55 56 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 57 58 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 59 60 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 61 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 62 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 63 64 /* TZ Address Space Controller Definitions */ 65 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 66 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 67 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 68 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 69 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 70 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 71 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 72 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 73 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 74 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 75 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 76 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 77 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 78 79 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 80 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 81 #define TP_ITYP_TYPE_ARM 0x0 82 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 83 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 84 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 85 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 86 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 87 #define TY_ITYP_VER_A7 0x1 88 #define TY_ITYP_VER_A53 0x2 89 #define TY_ITYP_VER_A57 0x3 90 91 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 92 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 93 #define TP_INIT_PER_CLUSTER 4 94 95 /* 96 * Define default values for some CCSR macros to make header files cleaner* 97 * 98 * To completely disable CCSR relocation in a board header file, define 99 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 100 * to a value that is the same as CONFIG_SYS_CCSRBAR. 101 */ 102 103 #ifdef CONFIG_SYS_CCSRBAR_PHYS 104 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 105 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 106 #endif 107 108 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 109 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 110 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 111 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 112 #endif 113 114 #ifndef CONFIG_SYS_CCSRBAR 115 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 116 #endif 117 118 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 119 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 120 #endif 121 122 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 123 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 124 #endif 125 126 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 127 CONFIG_SYS_CCSRBAR_PHYS_LOW) 128 129 struct sys_info { 130 unsigned long freq_processor[CONFIG_MAX_CPUS]; 131 unsigned long freq_systembus; 132 unsigned long freq_ddrbus; 133 unsigned long freq_localbus; 134 unsigned long freq_sdhc; 135 #ifdef CONFIG_SYS_DPAA_FMAN 136 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 137 #endif 138 unsigned long freq_qman; 139 }; 140 141 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 142 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 143 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 144 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 145 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 146 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 147 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 148 149 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 150 #define CONFIG_SYS_FSL_FM1_ADDR \ 151 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 152 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 153 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 154 155 /* Device Configuration and Pin Control */ 156 struct ccsr_gur { 157 u32 porsr1; /* POR status 1 */ 158 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 159 u32 porsr2; /* POR status 2 */ 160 u8 res_008[0x20-0x8]; 161 u32 gpporcr1; /* General-purpose POR configuration */ 162 u32 gpporcr2; 163 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 164 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 165 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 166 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 167 u32 dcfg_fusesr; /* Fuse status register */ 168 u8 res_02c[0x70-0x2c]; 169 u32 devdisr; /* Device disable control */ 170 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 171 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 172 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 173 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 174 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 175 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 176 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 177 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 178 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 179 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 180 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 181 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 182 u32 devdisr2; /* Device disable control 2 */ 183 u32 devdisr3; /* Device disable control 3 */ 184 u32 devdisr4; /* Device disable control 4 */ 185 u32 devdisr5; /* Device disable control 5 */ 186 u32 devdisr6; /* Device disable control 6 */ 187 u32 devdisr7; /* Device disable control 7 */ 188 u8 res_08c[0x94-0x8c]; 189 u32 coredisru; /* uppper portion for support of 64 cores */ 190 u32 coredisrl; /* lower portion for support of 64 cores */ 191 u8 res_09c[0xa0-0x9c]; 192 u32 pvr; /* Processor version */ 193 u32 svr; /* System version */ 194 u32 mvr; /* Manufacturing version */ 195 u8 res_0ac[0xb0-0xac]; 196 u32 rstcr; /* Reset control */ 197 u32 rstrqpblsr; /* Reset request preboot loader status */ 198 u8 res_0b8[0xc0-0xb8]; 199 u32 rstrqmr1; /* Reset request mask */ 200 u8 res_0c4[0xc8-0xc4]; 201 u32 rstrqsr1; /* Reset request status */ 202 u8 res_0cc[0xd4-0xcc]; 203 u32 rstrqwdtmrl; /* Reset request WDT mask */ 204 u8 res_0d8[0xdc-0xd8]; 205 u32 rstrqwdtsrl; /* Reset request WDT status */ 206 u8 res_0e0[0xe4-0xe0]; 207 u32 brrl; /* Boot release */ 208 u8 res_0e8[0x100-0xe8]; 209 u32 rcwsr[16]; /* Reset control word status */ 210 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 211 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 212 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 213 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 214 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 215 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 216 u8 res_140[0x200-0x140]; 217 u32 scratchrw[4]; /* Scratch Read/Write */ 218 u8 res_210[0x300-0x210]; 219 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 220 u8 res_310[0x400-0x310]; 221 u32 crstsr[12]; 222 u8 res_430[0x500-0x430]; 223 224 /* PCI Express n Logical I/O Device Number register */ 225 u32 dcfg_ccsr_pex1liodnr; 226 u32 dcfg_ccsr_pex2liodnr; 227 u32 dcfg_ccsr_pex3liodnr; 228 u32 dcfg_ccsr_pex4liodnr; 229 /* RIO n Logical I/O Device Number register */ 230 u32 dcfg_ccsr_rio1liodnr; 231 u32 dcfg_ccsr_rio2liodnr; 232 u32 dcfg_ccsr_rio3liodnr; 233 u32 dcfg_ccsr_rio4liodnr; 234 /* USB Logical I/O Device Number register */ 235 u32 dcfg_ccsr_usb1liodnr; 236 u32 dcfg_ccsr_usb2liodnr; 237 u32 dcfg_ccsr_usb3liodnr; 238 u32 dcfg_ccsr_usb4liodnr; 239 /* SD/MMC Logical I/O Device Number register */ 240 u32 dcfg_ccsr_sdmmc1liodnr; 241 u32 dcfg_ccsr_sdmmc2liodnr; 242 u32 dcfg_ccsr_sdmmc3liodnr; 243 u32 dcfg_ccsr_sdmmc4liodnr; 244 /* RIO Message Unit Logical I/O Device Number register */ 245 u32 dcfg_ccsr_riomaintliodnr; 246 247 u8 res_544[0x550-0x544]; 248 u32 sataliodnr[4]; 249 u8 res_560[0x570-0x560]; 250 251 u32 dcfg_ccsr_misc1liodnr; 252 u32 dcfg_ccsr_misc2liodnr; 253 u32 dcfg_ccsr_misc3liodnr; 254 u32 dcfg_ccsr_misc4liodnr; 255 u32 dcfg_ccsr_dma1liodnr; 256 u32 dcfg_ccsr_dma2liodnr; 257 u32 dcfg_ccsr_dma3liodnr; 258 u32 dcfg_ccsr_dma4liodnr; 259 u32 dcfg_ccsr_spare1liodnr; 260 u32 dcfg_ccsr_spare2liodnr; 261 u32 dcfg_ccsr_spare3liodnr; 262 u32 dcfg_ccsr_spare4liodnr; 263 u8 res_5a0[0x600-0x5a0]; 264 u32 dcfg_ccsr_pblsr; 265 266 u32 pamubypenr; 267 u32 dmacr1; 268 269 u8 res_60c[0x610-0x60c]; 270 u32 dcfg_ccsr_gensr1; 271 u32 dcfg_ccsr_gensr2; 272 u32 dcfg_ccsr_gensr3; 273 u32 dcfg_ccsr_gensr4; 274 u32 dcfg_ccsr_gencr1; 275 u32 dcfg_ccsr_gencr2; 276 u32 dcfg_ccsr_gencr3; 277 u32 dcfg_ccsr_gencr4; 278 u32 dcfg_ccsr_gencr5; 279 u32 dcfg_ccsr_gencr6; 280 u32 dcfg_ccsr_gencr7; 281 u8 res_63c[0x658-0x63c]; 282 u32 dcfg_ccsr_cgensr1; 283 u32 dcfg_ccsr_cgensr0; 284 u8 res_660[0x678-0x660]; 285 u32 dcfg_ccsr_cgencr1; 286 287 u32 dcfg_ccsr_cgencr0; 288 u8 res_680[0x700-0x680]; 289 u32 dcfg_ccsr_sriopstecr; 290 u32 dcfg_ccsr_dcsrcr; 291 292 u8 res_708[0x740-0x708]; /* add more registers when needed */ 293 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 294 struct { 295 u32 upper; 296 u32 lower; 297 } tp_cluster[16]; 298 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 299 u32 dcfg_ccsr_qmbm_warmrst; 300 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 301 u32 dcfg_ccsr_reserved0; 302 u32 dcfg_ccsr_reserved1; 303 }; 304 305 #define SCFG_QSPI_CLKSEL 0x40100000 306 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 307 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 308 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 309 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 310 #define SCFG_USBPWRFAULT_SHARED 0x00000001 311 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 312 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 313 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 314 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 315 316 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 317 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 318 319 /* Supplemental Configuration Unit */ 320 struct ccsr_scfg { 321 u8 res_000[0x100-0x000]; 322 u32 usb2_icid; 323 u32 usb3_icid; 324 u8 res_108[0x114-0x108]; 325 u32 dma_icid; 326 u32 sata_icid; 327 u32 usb1_icid; 328 u32 qe_icid; 329 u32 sdhc_icid; 330 u32 edma_icid; 331 u32 etr_icid; 332 u32 core_sft_rst[4]; 333 u8 res_140[0x158-0x140]; 334 u32 altcbar; 335 u32 qspi_cfg; 336 u8 res_160[0x180-0x160]; 337 u32 dmamcr; 338 u8 res_184[0x18c-0x184]; 339 u32 debug_icid; 340 u8 res_190[0x1a4-0x190]; 341 u32 snpcnfgcr; 342 u8 res_1a8[0x1ac-0x1a8]; 343 u32 intpcr; 344 u8 res_1b0[0x204-0x1b0]; 345 u32 coresrencr; 346 u8 res_208[0x220-0x208]; 347 u32 rvbar0_0; 348 u32 rvbar0_1; 349 u32 rvbar1_0; 350 u32 rvbar1_1; 351 u32 rvbar2_0; 352 u32 rvbar2_1; 353 u32 rvbar3_0; 354 u32 rvbar3_1; 355 u32 lpmcsr; 356 u8 res_244[0x400-0x244]; 357 u32 qspidqscr; 358 u32 ecgtxcmcr; 359 u32 sdhciovselcr; 360 u32 rcwpmuxcr0; 361 u32 usbdrvvbus_selcr; 362 u32 usbpwrfault_selcr; 363 u32 usb_refclk_selcr1; 364 u32 usb_refclk_selcr2; 365 u32 usb_refclk_selcr3; 366 u8 res_424[0x600-0x424]; 367 u32 scratchrw[4]; 368 u8 res_610[0x680-0x610]; 369 u32 corebcr; 370 u8 res_684[0x1000-0x684]; 371 u32 pex1msiir; 372 u32 pex1msir; 373 u8 res_1008[0x2000-0x1008]; 374 u32 pex2; 375 u32 pex2msir; 376 u8 res_2008[0x3000-0x2008]; 377 u32 pex3msiir; 378 u32 pex3msir; 379 }; 380 381 /* Clocking */ 382 struct ccsr_clk { 383 struct { 384 u32 clkcncsr; /* core cluster n clock control status */ 385 u8 res_004[0x0c]; 386 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 387 u8 res_014[0x0c]; 388 } clkcsr[4]; 389 u8 res_040[0x780]; /* 0x100 */ 390 struct { 391 u32 pllcngsr; 392 u8 res_804[0x1c]; 393 } pllcgsr[2]; 394 u8 res_840[0x1c0]; 395 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 396 u8 res_a04[0x1fc]; 397 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 398 u8 res_c04[0x1c]; 399 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 400 u8 res_c24[0x3dc]; 401 }; 402 403 /* System Counter */ 404 struct sctr_regs { 405 u32 cntcr; 406 u32 cntsr; 407 u32 cntcv1; 408 u32 cntcv2; 409 u32 resv1[4]; 410 u32 cntfid0; 411 u32 cntfid1; 412 u32 resv2[1002]; 413 u32 counterid[12]; 414 }; 415 416 #define SRDS_MAX_LANES 4 417 struct ccsr_serdes { 418 struct { 419 u32 rstctl; /* Reset Control Register */ 420 #define SRDS_RSTCTL_RST 0x80000000 421 #define SRDS_RSTCTL_RSTDONE 0x40000000 422 #define SRDS_RSTCTL_RSTERR 0x20000000 423 #define SRDS_RSTCTL_SWRST 0x10000000 424 #define SRDS_RSTCTL_SDEN 0x00000020 425 #define SRDS_RSTCTL_SDRST_B 0x00000040 426 #define SRDS_RSTCTL_PLLRST_B 0x00000080 427 u32 pllcr0; /* PLL Control Register 0 */ 428 #define SRDS_PLLCR0_POFF 0x80000000 429 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 430 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 431 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 432 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 433 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 434 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 435 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 436 #define SRDS_PLLCR0_PLL_LCK 0x00800000 437 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 438 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 439 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 440 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 441 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 442 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 443 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 444 u32 pllcr1; /* PLL Control Register 1 */ 445 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 446 u32 res_0c; /* 0x00c */ 447 u32 pllcr3; 448 u32 pllcr4; 449 u8 res_18[0x20-0x18]; 450 } bank[2]; 451 u8 res_40[0x90-0x40]; 452 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 453 u8 res_94[0xa0-0x94]; 454 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 455 u8 res_a4[0xb0-0xa4]; 456 u32 srdsgr0; /* 0xb0 General Register 0 */ 457 u8 res_b4[0xe0-0xb4]; 458 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 459 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 460 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 461 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 462 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 463 u8 res_f4[0x100-0xf4]; 464 struct { 465 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 466 u8 res_104[0x120-0x104]; 467 } srdslnpssr[4]; 468 u8 res_180[0x300-0x180]; 469 u32 srdspexeqcr; 470 u32 srdspexeqpcr[11]; 471 u8 res_330[0x400-0x330]; 472 u32 srdspexapcr; 473 u8 res_404[0x440-0x404]; 474 u32 srdspexbpcr; 475 u8 res_444[0x800-0x444]; 476 struct { 477 u32 gcr0; /* 0x800 General Control Register 0 */ 478 u32 gcr1; /* 0x804 General Control Register 1 */ 479 u32 gcr2; /* 0x808 General Control Register 2 */ 480 u32 sscr0; 481 u32 recr0; /* 0x810 Receive Equalization Control */ 482 u32 recr1; 483 u32 tecr0; /* 0x818 Transmit Equalization Control */ 484 u32 sscr1; 485 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 486 u8 res_824[0x83c-0x824]; 487 u32 tcsr3; 488 } lane[4]; /* Lane A, B, C, D, E, F, G, H */ 489 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 490 }; 491 492 #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 493 #define CCI400_CTRLORD_EN_BARRIER 0 494 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 495 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 496 #define CCI400_SNOOP_REQ_EN 0x00000001 497 498 /* CCI-400 registers */ 499 struct ccsr_cci400 { 500 u32 ctrl_ord; /* Control Override */ 501 u32 spec_ctrl; /* Speculation Control */ 502 u32 secure_access; /* Secure Access */ 503 u32 status; /* Status */ 504 u32 impr_err; /* Imprecise Error */ 505 u8 res_14[0x100 - 0x14]; 506 u32 pmcr; /* Performance Monitor Control */ 507 u8 res_104[0xfd0 - 0x104]; 508 u32 pid[8]; /* Peripheral ID */ 509 u32 cid[4]; /* Component ID */ 510 struct { 511 u32 snoop_ctrl; /* Snoop Control */ 512 u32 sha_ord; /* Shareable Override */ 513 u8 res_1008[0x1100 - 0x1008]; 514 u32 rc_qos_ord; /* read channel QoS Value Override */ 515 u32 wc_qos_ord; /* read channel QoS Value Override */ 516 u8 res_1108[0x110c - 0x1108]; 517 u32 qos_ctrl; /* QoS Control */ 518 u32 max_ot; /* Max OT */ 519 u8 res_1114[0x1130 - 0x1114]; 520 u32 target_lat; /* Target Latency */ 521 u32 latency_regu; /* Latency Regulation */ 522 u32 qos_range; /* QoS Range */ 523 u8 res_113c[0x2000 - 0x113c]; 524 } slave[5]; /* Slave Interface */ 525 u8 res_6000[0x9004 - 0x6000]; 526 u32 cycle_counter; /* Cycle counter */ 527 u32 count_ctrl; /* Count Control */ 528 u32 overflow_status; /* Overflow Flag Status */ 529 u8 res_9010[0xa000 - 0x9010]; 530 struct { 531 u32 event_select; /* Event Select */ 532 u32 event_count; /* Event Count */ 533 u32 counter_ctrl; /* Counter Control */ 534 u32 overflow_status; /* Overflow Flag Status */ 535 u8 res_a010[0xb000 - 0xa010]; 536 } pcounter[4]; /* Performance Counter */ 537 u8 res_e004[0x10000 - 0xe004]; 538 }; 539 540 /* MMU 500 */ 541 #define SMMU_SCR0 (SMMU_BASE + 0x0) 542 #define SMMU_SCR1 (SMMU_BASE + 0x4) 543 #define SMMU_SCR2 (SMMU_BASE + 0x8) 544 #define SMMU_SACR (SMMU_BASE + 0x10) 545 #define SMMU_IDR0 (SMMU_BASE + 0x20) 546 #define SMMU_IDR1 (SMMU_BASE + 0x24) 547 548 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 549 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 550 #define SMMU_NSACR (SMMU_BASE + 0x410) 551 552 #define SCR0_CLIENTPD_MASK 0x00000001 553 #define SCR0_USFCFG_MASK 0x00000400 554 555 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 556