1 /* 2 * Copyright 2013-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 8 #define __ARCH_FSL_LSCH2_IMMAP_H__ 9 10 #include <fsl_immap.h> 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_DCSRBAR 0x20000000 14 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) 16 17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 18 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 19 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 20 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 21 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 22 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 23 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 24 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 25 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 26 #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) 27 #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) 28 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 29 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 30 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 31 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 32 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 33 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 34 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 35 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 36 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 37 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 38 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 39 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 40 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 41 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 42 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 43 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 44 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 45 46 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 47 #define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 48 #define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ 49 CONFIG_SYS_BMAN_MEM_BASE) 50 #define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 51 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 52 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 53 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 54 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 55 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 56 CONFIG_SYS_BMAN_CENA_SIZE) 57 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 58 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 59 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 60 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 61 #define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \ 62 CONFIG_SYS_QMAN_MEM_BASE) 63 #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 64 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 65 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 66 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 67 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 68 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 69 CONFIG_SYS_QMAN_CENA_SIZE) 70 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 71 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 72 73 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 74 75 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 76 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 77 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 78 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 79 80 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 81 82 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 83 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 84 85 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 86 87 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 88 89 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 90 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 91 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 92 /* LUT registers */ 93 #ifdef CONFIG_ARCH_LS1012A 94 #define PCIE_LUT_BASE 0xC0000 95 #else 96 #define PCIE_LUT_BASE 0x10000 97 #endif 98 #define PCIE_LUT_LCTRL0 0x7F8 99 #define PCIE_LUT_DBG 0x7FC 100 101 /* TZ Address Space Controller Definitions */ 102 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 103 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 104 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 105 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 106 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 107 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 108 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 109 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 110 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 111 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 112 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 113 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 114 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 115 116 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 117 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 118 #define TP_ITYP_TYPE_ARM 0x0 119 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 120 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 121 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 122 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 123 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 124 #define TY_ITYP_VER_A7 0x1 125 #define TY_ITYP_VER_A53 0x2 126 #define TY_ITYP_VER_A57 0x3 127 #define TY_ITYP_VER_A72 0x4 128 129 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 130 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 131 #define TP_INIT_PER_CLUSTER 4 132 133 /* 134 * Define default values for some CCSR macros to make header files cleaner* 135 * 136 * To completely disable CCSR relocation in a board header file, define 137 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 138 * to a value that is the same as CONFIG_SYS_CCSRBAR. 139 */ 140 141 #ifdef CONFIG_SYS_CCSRBAR_PHYS 142 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 143 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 144 #endif 145 146 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 147 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 148 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 149 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 150 #endif 151 152 #ifndef CONFIG_SYS_CCSRBAR 153 #define CONFIG_SYS_CCSRBAR 0x01000000 154 #endif 155 156 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 157 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 158 #endif 159 160 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 161 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 162 #endif 163 164 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 165 CONFIG_SYS_CCSRBAR_PHYS_LOW) 166 167 struct sys_info { 168 unsigned long freq_processor[CONFIG_MAX_CPUS]; 169 /* frequency of platform PLL */ 170 unsigned long freq_systembus; 171 unsigned long freq_ddrbus; 172 unsigned long freq_localbus; 173 unsigned long freq_sdhc; 174 #ifdef CONFIG_SYS_DPAA_FMAN 175 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 176 #endif 177 unsigned long freq_qman; 178 }; 179 180 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 181 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 182 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 183 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 184 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 185 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 186 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 187 188 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 189 #define CONFIG_SYS_FSL_FM1_ADDR \ 190 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 191 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 192 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 193 194 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull 195 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull 196 #define CONFIG_SYS_FSL_SEC_ADDR \ 197 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 198 #define CONFIG_SYS_FSL_JR0_ADDR \ 199 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 200 201 /* Device Configuration and Pin Control */ 202 #define DCFG_DCSR_PORCR1 0x0 203 204 struct ccsr_gur { 205 u32 porsr1; /* POR status 1 */ 206 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 207 u32 porsr2; /* POR status 2 */ 208 u8 res_008[0x20-0x8]; 209 u32 gpporcr1; /* General-purpose POR configuration */ 210 u32 gpporcr2; 211 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 212 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 213 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 214 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 215 u32 dcfg_fusesr; /* Fuse status register */ 216 u8 res_02c[0x70-0x2c]; 217 u32 devdisr; /* Device disable control */ 218 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 219 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 220 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 221 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 222 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 223 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 224 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 225 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 226 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 227 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 228 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 229 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 230 u32 devdisr2; /* Device disable control 2 */ 231 u32 devdisr3; /* Device disable control 3 */ 232 u32 devdisr4; /* Device disable control 4 */ 233 u32 devdisr5; /* Device disable control 5 */ 234 u32 devdisr6; /* Device disable control 6 */ 235 u32 devdisr7; /* Device disable control 7 */ 236 u8 res_08c[0x94-0x8c]; 237 u32 coredisru; /* uppper portion for support of 64 cores */ 238 u32 coredisrl; /* lower portion for support of 64 cores */ 239 u8 res_09c[0xa0-0x9c]; 240 u32 pvr; /* Processor version */ 241 u32 svr; /* System version */ 242 u32 mvr; /* Manufacturing version */ 243 u8 res_0ac[0xb0-0xac]; 244 u32 rstcr; /* Reset control */ 245 u32 rstrqpblsr; /* Reset request preboot loader status */ 246 u8 res_0b8[0xc0-0xb8]; 247 u32 rstrqmr1; /* Reset request mask */ 248 u8 res_0c4[0xc8-0xc4]; 249 u32 rstrqsr1; /* Reset request status */ 250 u8 res_0cc[0xd4-0xcc]; 251 u32 rstrqwdtmrl; /* Reset request WDT mask */ 252 u8 res_0d8[0xdc-0xd8]; 253 u32 rstrqwdtsrl; /* Reset request WDT status */ 254 u8 res_0e0[0xe4-0xe0]; 255 u32 brrl; /* Boot release */ 256 u8 res_0e8[0x100-0xe8]; 257 u32 rcwsr[16]; /* Reset control word status */ 258 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 259 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 260 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 261 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 262 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 263 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 264 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 265 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 266 #define RCW_SB_EN_REG_INDEX 7 267 #define RCW_SB_EN_MASK 0x00200000 268 269 u8 res_140[0x200-0x140]; 270 u32 scratchrw[4]; /* Scratch Read/Write */ 271 u8 res_210[0x300-0x210]; 272 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 273 u8 res_310[0x400-0x310]; 274 u32 crstsr[12]; 275 u8 res_430[0x500-0x430]; 276 277 /* PCI Express n Logical I/O Device Number register */ 278 u32 dcfg_ccsr_pex1liodnr; 279 u32 dcfg_ccsr_pex2liodnr; 280 u32 dcfg_ccsr_pex3liodnr; 281 u32 dcfg_ccsr_pex4liodnr; 282 /* RIO n Logical I/O Device Number register */ 283 u32 dcfg_ccsr_rio1liodnr; 284 u32 dcfg_ccsr_rio2liodnr; 285 u32 dcfg_ccsr_rio3liodnr; 286 u32 dcfg_ccsr_rio4liodnr; 287 /* USB Logical I/O Device Number register */ 288 u32 dcfg_ccsr_usb1liodnr; 289 u32 dcfg_ccsr_usb2liodnr; 290 u32 dcfg_ccsr_usb3liodnr; 291 u32 dcfg_ccsr_usb4liodnr; 292 /* SD/MMC Logical I/O Device Number register */ 293 u32 dcfg_ccsr_sdmmc1liodnr; 294 u32 dcfg_ccsr_sdmmc2liodnr; 295 u32 dcfg_ccsr_sdmmc3liodnr; 296 u32 dcfg_ccsr_sdmmc4liodnr; 297 /* RIO Message Unit Logical I/O Device Number register */ 298 u32 dcfg_ccsr_riomaintliodnr; 299 300 u8 res_544[0x550-0x544]; 301 u32 sataliodnr[4]; 302 u8 res_560[0x570-0x560]; 303 304 u32 dcfg_ccsr_misc1liodnr; 305 u32 dcfg_ccsr_misc2liodnr; 306 u32 dcfg_ccsr_misc3liodnr; 307 u32 dcfg_ccsr_misc4liodnr; 308 u32 dcfg_ccsr_dma1liodnr; 309 u32 dcfg_ccsr_dma2liodnr; 310 u32 dcfg_ccsr_dma3liodnr; 311 u32 dcfg_ccsr_dma4liodnr; 312 u32 dcfg_ccsr_spare1liodnr; 313 u32 dcfg_ccsr_spare2liodnr; 314 u32 dcfg_ccsr_spare3liodnr; 315 u32 dcfg_ccsr_spare4liodnr; 316 u8 res_5a0[0x600-0x5a0]; 317 u32 dcfg_ccsr_pblsr; 318 319 u32 pamubypenr; 320 u32 dmacr1; 321 322 u8 res_60c[0x610-0x60c]; 323 u32 dcfg_ccsr_gensr1; 324 u32 dcfg_ccsr_gensr2; 325 u32 dcfg_ccsr_gensr3; 326 u32 dcfg_ccsr_gensr4; 327 u32 dcfg_ccsr_gencr1; 328 u32 dcfg_ccsr_gencr2; 329 u32 dcfg_ccsr_gencr3; 330 u32 dcfg_ccsr_gencr4; 331 u32 dcfg_ccsr_gencr5; 332 u32 dcfg_ccsr_gencr6; 333 u32 dcfg_ccsr_gencr7; 334 u8 res_63c[0x658-0x63c]; 335 u32 dcfg_ccsr_cgensr1; 336 u32 dcfg_ccsr_cgensr0; 337 u8 res_660[0x678-0x660]; 338 u32 dcfg_ccsr_cgencr1; 339 340 u32 dcfg_ccsr_cgencr0; 341 u8 res_680[0x700-0x680]; 342 u32 dcfg_ccsr_sriopstecr; 343 u32 dcfg_ccsr_dcsrcr; 344 345 u8 res_708[0x740-0x708]; /* add more registers when needed */ 346 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 347 struct { 348 u32 upper; 349 u32 lower; 350 } tp_cluster[16]; 351 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 352 u32 dcfg_ccsr_qmbm_warmrst; 353 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 354 u32 dcfg_ccsr_reserved0; 355 u32 dcfg_ccsr_reserved1; 356 }; 357 358 #define SCFG_QSPI_CLKSEL 0x40100000 359 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 360 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 361 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 362 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 363 #define SCFG_USBPWRFAULT_SHARED 0x00000001 364 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 365 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 366 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 367 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 368 369 #define SCFG_BASE 0x01570000 370 #define SCFG_USB3PRM1CR_USB1 0x070 371 #define SCFG_USB3PRM2CR_USB1 0x074 372 #define SCFG_USB3PRM1CR_USB2 0x07C 373 #define SCFG_USB3PRM2CR_USB2 0x080 374 #define SCFG_USB3PRM1CR_USB3 0x088 375 #define SCFG_USB3PRM2CR_USB3 0x08c 376 #define SCFG_USB_TXVREFTUNE 0x9 377 #define SCFG_USB_SQRXTUNE_MASK 0x7 378 #define SCFG_USB_PCSTXSWINGFULL 0x47 379 #define SCFG_USB_PHY1 0x084F0000 380 #define SCFG_USB_PHY2 0x08500000 381 #define SCFG_USB_PHY3 0x08510000 382 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 383 #define USB_PHY_RX_EQ_VAL_1 0x0000 384 #define USB_PHY_RX_EQ_VAL_2 0x0080 385 #define USB_PHY_RX_EQ_VAL_3 0x0380 386 #define USB_PHY_RX_EQ_VAL_4 0x0b80 387 388 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 389 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 390 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 391 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 392 393 /* Supplemental Configuration Unit */ 394 struct ccsr_scfg { 395 u8 res_000[0x100-0x000]; 396 u32 usb2_icid; 397 u32 usb3_icid; 398 u8 res_108[0x114-0x108]; 399 u32 dma_icid; 400 u32 sata_icid; 401 u32 usb1_icid; 402 u32 qe_icid; 403 u32 sdhc_icid; 404 u32 edma_icid; 405 u32 etr_icid; 406 u32 core_sft_rst[4]; 407 u8 res_140[0x158-0x140]; 408 u32 altcbar; 409 u32 qspi_cfg; 410 u8 res_160[0x180-0x160]; 411 u32 dmamcr; 412 u8 res_184[0x188-0x184]; 413 u32 gic_align; 414 u32 debug_icid; 415 u8 res_190[0x1a4-0x190]; 416 u32 snpcnfgcr; 417 u8 res_1a8[0x1ac-0x1a8]; 418 u32 intpcr; 419 u8 res_1b0[0x204-0x1b0]; 420 u32 coresrencr; 421 u8 res_208[0x220-0x208]; 422 u32 rvbar0_0; 423 u32 rvbar0_1; 424 u32 rvbar1_0; 425 u32 rvbar1_1; 426 u32 rvbar2_0; 427 u32 rvbar2_1; 428 u32 rvbar3_0; 429 u32 rvbar3_1; 430 u32 lpmcsr; 431 u8 res_244[0x400-0x244]; 432 u32 qspidqscr; 433 u32 ecgtxcmcr; 434 u32 sdhciovselcr; 435 u32 rcwpmuxcr0; 436 u32 usbdrvvbus_selcr; 437 u32 usbpwrfault_selcr; 438 u32 usb_refclk_selcr1; 439 u32 usb_refclk_selcr2; 440 u32 usb_refclk_selcr3; 441 u8 res_424[0x600-0x424]; 442 u32 scratchrw[4]; 443 u8 res_610[0x680-0x610]; 444 u32 corebcr; 445 u8 res_684[0x1000-0x684]; 446 u32 pex1msiir; 447 u32 pex1msir; 448 u8 res_1008[0x2000-0x1008]; 449 u32 pex2; 450 u32 pex2msir; 451 u8 res_2008[0x3000-0x2008]; 452 u32 pex3msiir; 453 u32 pex3msir; 454 }; 455 456 /* Clocking */ 457 struct ccsr_clk { 458 struct { 459 u32 clkcncsr; /* core cluster n clock control status */ 460 u8 res_004[0x0c]; 461 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 462 u8 res_014[0x0c]; 463 } clkcsr[4]; 464 u8 res_040[0x780]; /* 0x100 */ 465 struct { 466 u32 pllcngsr; 467 u8 res_804[0x1c]; 468 } pllcgsr[2]; 469 u8 res_840[0x1c0]; 470 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 471 u8 res_a04[0x1fc]; 472 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 473 u8 res_c04[0x1c]; 474 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 475 u8 res_c24[0x3dc]; 476 }; 477 478 /* System Counter */ 479 struct sctr_regs { 480 u32 cntcr; 481 u32 cntsr; 482 u32 cntcv1; 483 u32 cntcv2; 484 u32 resv1[4]; 485 u32 cntfid0; 486 u32 cntfid1; 487 u32 resv2[1002]; 488 u32 counterid[12]; 489 }; 490 491 #define SRDS_MAX_LANES 4 492 struct ccsr_serdes { 493 struct { 494 u32 rstctl; /* Reset Control Register */ 495 #define SRDS_RSTCTL_RST 0x80000000 496 #define SRDS_RSTCTL_RSTDONE 0x40000000 497 #define SRDS_RSTCTL_RSTERR 0x20000000 498 #define SRDS_RSTCTL_SWRST 0x10000000 499 #define SRDS_RSTCTL_SDEN 0x00000020 500 #define SRDS_RSTCTL_SDRST_B 0x00000040 501 #define SRDS_RSTCTL_PLLRST_B 0x00000080 502 u32 pllcr0; /* PLL Control Register 0 */ 503 #define SRDS_PLLCR0_POFF 0x80000000 504 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 505 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 506 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 507 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 508 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 509 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 510 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 511 #define SRDS_PLLCR0_PLL_LCK 0x00800000 512 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 513 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 514 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 515 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 516 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 517 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 518 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 519 u32 pllcr1; /* PLL Control Register 1 */ 520 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 521 u32 res_0c; /* 0x00c */ 522 u32 pllcr3; 523 u32 pllcr4; 524 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 525 u8 res_1c[0x20-0x1c]; 526 } bank[2]; 527 u8 res_40[0x90-0x40]; 528 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 529 u8 res_94[0xa0-0x94]; 530 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 531 u8 res_a4[0xb0-0xa4]; 532 u32 srdsgr0; /* 0xb0 General Register 0 */ 533 u8 res_b4[0x100-0xb4]; 534 struct { 535 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 536 u8 res_104[0x120-0x104]; 537 } lnpssr[4]; /* Lane A, B, C, D */ 538 u8 res_180[0x200-0x180]; 539 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 540 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 541 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 542 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 543 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 544 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 545 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 546 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 547 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 548 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 549 u32 srdspccra; /* 0x228 Protocol Configuration A */ 550 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 551 u8 res_230[0x800-0x230]; 552 struct { 553 u32 gcr0; /* 0x800 General Control Register 0 */ 554 u32 gcr1; /* 0x804 General Control Register 1 */ 555 u32 gcr2; /* 0x808 General Control Register 2 */ 556 u32 sscr0; 557 u32 recr0; /* 0x810 Receive Equalization Control */ 558 u32 recr1; 559 u32 tecr0; /* 0x818 Transmit Equalization Control */ 560 u32 sscr1; 561 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 562 u8 res_824[0x83c-0x824]; 563 u32 tcsr3; 564 } lane[4]; /* Lane A, B, C, D */ 565 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 566 struct { 567 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 568 u8 res_1004[0x1040-0x1004]; 569 } pcie[3]; 570 u8 res_10c0[0x1800-0x10c0]; 571 struct { 572 u8 res_1800[0x1804-0x1800]; 573 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 574 u8 res_1808[0x180c-0x1808]; 575 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 576 } sgmii[4]; /* Lane A, B, C, D */ 577 u8 res_1840[0x1880-0x1840]; 578 struct { 579 u8 res_1880[0x1884-0x1880]; 580 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 581 u8 res_1888[0x188c-0x1888]; 582 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 583 } qsgmii[2]; /* Lane A, B */ 584 u8 res_18a0[0x1980-0x18a0]; 585 struct { 586 u8 res_1980[0x1984-0x1980]; 587 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 588 u8 res_1988[0x198c-0x1988]; 589 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 590 } xfi[2]; /* Lane A, B */ 591 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 592 }; 593 594 /* MMU 500 */ 595 #define SMMU_SCR0 (SMMU_BASE + 0x0) 596 #define SMMU_SCR1 (SMMU_BASE + 0x4) 597 #define SMMU_SCR2 (SMMU_BASE + 0x8) 598 #define SMMU_SACR (SMMU_BASE + 0x10) 599 #define SMMU_IDR0 (SMMU_BASE + 0x20) 600 #define SMMU_IDR1 (SMMU_BASE + 0x24) 601 602 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 603 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 604 #define SMMU_NSACR (SMMU_BASE + 0x410) 605 606 #define SCR0_CLIENTPD_MASK 0x00000001 607 #define SCR0_USFCFG_MASK 0x00000400 608 609 uint get_svr(void); 610 611 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 612