1 /* 2 * Copyright 2013-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 8 #define __ARCH_FSL_LSCH2_IMMAP_H__ 9 10 #include <fsl_immap.h> 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_DCSRBAR 0x20000000 14 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) 16 17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 18 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) 19 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 20 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 21 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 22 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 23 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 24 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 25 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 26 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 27 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 28 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 29 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 30 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 31 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 32 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 33 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 34 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 35 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 36 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 37 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 38 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 39 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 40 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 41 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 42 43 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 44 45 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 46 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 47 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 48 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 49 50 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 51 52 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 53 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 54 55 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 56 57 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 58 59 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 60 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 61 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 62 /* LUT registers */ 63 #ifdef CONFIG_LS1012A 64 #define PCIE_LUT_BASE 0xC0000 65 #else 66 #define PCIE_LUT_BASE 0x10000 67 #endif 68 #define PCIE_LUT_LCTRL0 0x7F8 69 #define PCIE_LUT_DBG 0x7FC 70 71 /* TZ Address Space Controller Definitions */ 72 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 73 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 74 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 75 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 76 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 77 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 78 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 79 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 80 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 81 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 82 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 83 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 84 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 85 86 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 87 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 88 #define TP_ITYP_TYPE_ARM 0x0 89 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 90 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 91 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 92 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 93 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 94 #define TY_ITYP_VER_A7 0x1 95 #define TY_ITYP_VER_A53 0x2 96 #define TY_ITYP_VER_A57 0x3 97 #define TY_ITYP_VER_A72 0x4 98 99 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 100 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 101 #define TP_INIT_PER_CLUSTER 4 102 103 /* 104 * Define default values for some CCSR macros to make header files cleaner* 105 * 106 * To completely disable CCSR relocation in a board header file, define 107 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 108 * to a value that is the same as CONFIG_SYS_CCSRBAR. 109 */ 110 111 #ifdef CONFIG_SYS_CCSRBAR_PHYS 112 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 113 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 114 #endif 115 116 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 117 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 118 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 119 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 120 #endif 121 122 #ifndef CONFIG_SYS_CCSRBAR 123 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 124 #endif 125 126 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 127 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 128 #endif 129 130 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 131 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 132 #endif 133 134 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 135 CONFIG_SYS_CCSRBAR_PHYS_LOW) 136 137 struct sys_info { 138 unsigned long freq_processor[CONFIG_MAX_CPUS]; 139 unsigned long freq_systembus; 140 unsigned long freq_ddrbus; 141 unsigned long freq_localbus; 142 unsigned long freq_sdhc; 143 #ifdef CONFIG_SYS_DPAA_FMAN 144 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 145 #endif 146 unsigned long freq_qman; 147 }; 148 149 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 150 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 151 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 152 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 153 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 154 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 155 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 156 157 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 158 #define CONFIG_SYS_FSL_FM1_ADDR \ 159 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 160 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 161 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 162 163 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull 164 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull 165 #define CONFIG_SYS_FSL_SEC_ADDR \ 166 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 167 #define CONFIG_SYS_FSL_JR0_ADDR \ 168 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 169 170 /* Device Configuration and Pin Control */ 171 struct ccsr_gur { 172 u32 porsr1; /* POR status 1 */ 173 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 174 u32 porsr2; /* POR status 2 */ 175 u8 res_008[0x20-0x8]; 176 u32 gpporcr1; /* General-purpose POR configuration */ 177 u32 gpporcr2; 178 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 179 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 180 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 181 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 182 u32 dcfg_fusesr; /* Fuse status register */ 183 u8 res_02c[0x70-0x2c]; 184 u32 devdisr; /* Device disable control */ 185 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 186 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 187 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 188 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 189 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 190 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 191 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 192 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 193 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 194 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 195 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 196 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 197 u32 devdisr2; /* Device disable control 2 */ 198 u32 devdisr3; /* Device disable control 3 */ 199 u32 devdisr4; /* Device disable control 4 */ 200 u32 devdisr5; /* Device disable control 5 */ 201 u32 devdisr6; /* Device disable control 6 */ 202 u32 devdisr7; /* Device disable control 7 */ 203 u8 res_08c[0x94-0x8c]; 204 u32 coredisru; /* uppper portion for support of 64 cores */ 205 u32 coredisrl; /* lower portion for support of 64 cores */ 206 u8 res_09c[0xa0-0x9c]; 207 u32 pvr; /* Processor version */ 208 u32 svr; /* System version */ 209 u32 mvr; /* Manufacturing version */ 210 u8 res_0ac[0xb0-0xac]; 211 u32 rstcr; /* Reset control */ 212 u32 rstrqpblsr; /* Reset request preboot loader status */ 213 u8 res_0b8[0xc0-0xb8]; 214 u32 rstrqmr1; /* Reset request mask */ 215 u8 res_0c4[0xc8-0xc4]; 216 u32 rstrqsr1; /* Reset request status */ 217 u8 res_0cc[0xd4-0xcc]; 218 u32 rstrqwdtmrl; /* Reset request WDT mask */ 219 u8 res_0d8[0xdc-0xd8]; 220 u32 rstrqwdtsrl; /* Reset request WDT status */ 221 u8 res_0e0[0xe4-0xe0]; 222 u32 brrl; /* Boot release */ 223 u8 res_0e8[0x100-0xe8]; 224 u32 rcwsr[16]; /* Reset control word status */ 225 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 226 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 227 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 228 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 229 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 230 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 231 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 232 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 233 #define RCW_SB_EN_REG_INDEX 7 234 #define RCW_SB_EN_MASK 0x00200000 235 236 u8 res_140[0x200-0x140]; 237 u32 scratchrw[4]; /* Scratch Read/Write */ 238 u8 res_210[0x300-0x210]; 239 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 240 u8 res_310[0x400-0x310]; 241 u32 crstsr[12]; 242 u8 res_430[0x500-0x430]; 243 244 /* PCI Express n Logical I/O Device Number register */ 245 u32 dcfg_ccsr_pex1liodnr; 246 u32 dcfg_ccsr_pex2liodnr; 247 u32 dcfg_ccsr_pex3liodnr; 248 u32 dcfg_ccsr_pex4liodnr; 249 /* RIO n Logical I/O Device Number register */ 250 u32 dcfg_ccsr_rio1liodnr; 251 u32 dcfg_ccsr_rio2liodnr; 252 u32 dcfg_ccsr_rio3liodnr; 253 u32 dcfg_ccsr_rio4liodnr; 254 /* USB Logical I/O Device Number register */ 255 u32 dcfg_ccsr_usb1liodnr; 256 u32 dcfg_ccsr_usb2liodnr; 257 u32 dcfg_ccsr_usb3liodnr; 258 u32 dcfg_ccsr_usb4liodnr; 259 /* SD/MMC Logical I/O Device Number register */ 260 u32 dcfg_ccsr_sdmmc1liodnr; 261 u32 dcfg_ccsr_sdmmc2liodnr; 262 u32 dcfg_ccsr_sdmmc3liodnr; 263 u32 dcfg_ccsr_sdmmc4liodnr; 264 /* RIO Message Unit Logical I/O Device Number register */ 265 u32 dcfg_ccsr_riomaintliodnr; 266 267 u8 res_544[0x550-0x544]; 268 u32 sataliodnr[4]; 269 u8 res_560[0x570-0x560]; 270 271 u32 dcfg_ccsr_misc1liodnr; 272 u32 dcfg_ccsr_misc2liodnr; 273 u32 dcfg_ccsr_misc3liodnr; 274 u32 dcfg_ccsr_misc4liodnr; 275 u32 dcfg_ccsr_dma1liodnr; 276 u32 dcfg_ccsr_dma2liodnr; 277 u32 dcfg_ccsr_dma3liodnr; 278 u32 dcfg_ccsr_dma4liodnr; 279 u32 dcfg_ccsr_spare1liodnr; 280 u32 dcfg_ccsr_spare2liodnr; 281 u32 dcfg_ccsr_spare3liodnr; 282 u32 dcfg_ccsr_spare4liodnr; 283 u8 res_5a0[0x600-0x5a0]; 284 u32 dcfg_ccsr_pblsr; 285 286 u32 pamubypenr; 287 u32 dmacr1; 288 289 u8 res_60c[0x610-0x60c]; 290 u32 dcfg_ccsr_gensr1; 291 u32 dcfg_ccsr_gensr2; 292 u32 dcfg_ccsr_gensr3; 293 u32 dcfg_ccsr_gensr4; 294 u32 dcfg_ccsr_gencr1; 295 u32 dcfg_ccsr_gencr2; 296 u32 dcfg_ccsr_gencr3; 297 u32 dcfg_ccsr_gencr4; 298 u32 dcfg_ccsr_gencr5; 299 u32 dcfg_ccsr_gencr6; 300 u32 dcfg_ccsr_gencr7; 301 u8 res_63c[0x658-0x63c]; 302 u32 dcfg_ccsr_cgensr1; 303 u32 dcfg_ccsr_cgensr0; 304 u8 res_660[0x678-0x660]; 305 u32 dcfg_ccsr_cgencr1; 306 307 u32 dcfg_ccsr_cgencr0; 308 u8 res_680[0x700-0x680]; 309 u32 dcfg_ccsr_sriopstecr; 310 u32 dcfg_ccsr_dcsrcr; 311 312 u8 res_708[0x740-0x708]; /* add more registers when needed */ 313 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 314 struct { 315 u32 upper; 316 u32 lower; 317 } tp_cluster[16]; 318 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 319 u32 dcfg_ccsr_qmbm_warmrst; 320 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 321 u32 dcfg_ccsr_reserved0; 322 u32 dcfg_ccsr_reserved1; 323 }; 324 325 #define SCFG_QSPI_CLKSEL 0x40100000 326 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 327 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 328 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 329 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 330 #define SCFG_USBPWRFAULT_SHARED 0x00000001 331 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 332 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 333 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 334 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 335 336 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 337 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 338 339 /* Supplemental Configuration Unit */ 340 struct ccsr_scfg { 341 u8 res_000[0x100-0x000]; 342 u32 usb2_icid; 343 u32 usb3_icid; 344 u8 res_108[0x114-0x108]; 345 u32 dma_icid; 346 u32 sata_icid; 347 u32 usb1_icid; 348 u32 qe_icid; 349 u32 sdhc_icid; 350 u32 edma_icid; 351 u32 etr_icid; 352 u32 core_sft_rst[4]; 353 u8 res_140[0x158-0x140]; 354 u32 altcbar; 355 u32 qspi_cfg; 356 u8 res_160[0x180-0x160]; 357 u32 dmamcr; 358 u8 res_184[0x18c-0x184]; 359 u32 debug_icid; 360 u8 res_190[0x1a4-0x190]; 361 u32 snpcnfgcr; 362 u8 res_1a8[0x1ac-0x1a8]; 363 u32 intpcr; 364 u8 res_1b0[0x204-0x1b0]; 365 u32 coresrencr; 366 u8 res_208[0x220-0x208]; 367 u32 rvbar0_0; 368 u32 rvbar0_1; 369 u32 rvbar1_0; 370 u32 rvbar1_1; 371 u32 rvbar2_0; 372 u32 rvbar2_1; 373 u32 rvbar3_0; 374 u32 rvbar3_1; 375 u32 lpmcsr; 376 u8 res_244[0x400-0x244]; 377 u32 qspidqscr; 378 u32 ecgtxcmcr; 379 u32 sdhciovselcr; 380 u32 rcwpmuxcr0; 381 u32 usbdrvvbus_selcr; 382 u32 usbpwrfault_selcr; 383 u32 usb_refclk_selcr1; 384 u32 usb_refclk_selcr2; 385 u32 usb_refclk_selcr3; 386 u8 res_424[0x600-0x424]; 387 u32 scratchrw[4]; 388 u8 res_610[0x680-0x610]; 389 u32 corebcr; 390 u8 res_684[0x1000-0x684]; 391 u32 pex1msiir; 392 u32 pex1msir; 393 u8 res_1008[0x2000-0x1008]; 394 u32 pex2; 395 u32 pex2msir; 396 u8 res_2008[0x3000-0x2008]; 397 u32 pex3msiir; 398 u32 pex3msir; 399 }; 400 401 /* Clocking */ 402 struct ccsr_clk { 403 struct { 404 u32 clkcncsr; /* core cluster n clock control status */ 405 u8 res_004[0x0c]; 406 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 407 u8 res_014[0x0c]; 408 } clkcsr[4]; 409 u8 res_040[0x780]; /* 0x100 */ 410 struct { 411 u32 pllcngsr; 412 u8 res_804[0x1c]; 413 } pllcgsr[2]; 414 u8 res_840[0x1c0]; 415 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 416 u8 res_a04[0x1fc]; 417 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 418 u8 res_c04[0x1c]; 419 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 420 u8 res_c24[0x3dc]; 421 }; 422 423 /* System Counter */ 424 struct sctr_regs { 425 u32 cntcr; 426 u32 cntsr; 427 u32 cntcv1; 428 u32 cntcv2; 429 u32 resv1[4]; 430 u32 cntfid0; 431 u32 cntfid1; 432 u32 resv2[1002]; 433 u32 counterid[12]; 434 }; 435 436 #define SRDS_MAX_LANES 4 437 struct ccsr_serdes { 438 struct { 439 u32 rstctl; /* Reset Control Register */ 440 #define SRDS_RSTCTL_RST 0x80000000 441 #define SRDS_RSTCTL_RSTDONE 0x40000000 442 #define SRDS_RSTCTL_RSTERR 0x20000000 443 #define SRDS_RSTCTL_SWRST 0x10000000 444 #define SRDS_RSTCTL_SDEN 0x00000020 445 #define SRDS_RSTCTL_SDRST_B 0x00000040 446 #define SRDS_RSTCTL_PLLRST_B 0x00000080 447 u32 pllcr0; /* PLL Control Register 0 */ 448 #define SRDS_PLLCR0_POFF 0x80000000 449 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 450 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 451 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 452 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 453 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 454 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 455 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 456 #define SRDS_PLLCR0_PLL_LCK 0x00800000 457 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 458 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 459 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 460 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 461 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 462 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 463 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 464 u32 pllcr1; /* PLL Control Register 1 */ 465 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 466 u32 res_0c; /* 0x00c */ 467 u32 pllcr3; 468 u32 pllcr4; 469 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 470 u8 res_1c[0x20-0x1c]; 471 } bank[2]; 472 u8 res_40[0x90-0x40]; 473 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 474 u8 res_94[0xa0-0x94]; 475 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 476 u8 res_a4[0xb0-0xa4]; 477 u32 srdsgr0; /* 0xb0 General Register 0 */ 478 u8 res_b4[0x100-0xb4]; 479 struct { 480 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 481 u8 res_104[0x120-0x104]; 482 } lnpssr[4]; /* Lane A, B, C, D */ 483 u8 res_180[0x200-0x180]; 484 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 485 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 486 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 487 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 488 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 489 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 490 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 491 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 492 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 493 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 494 u32 srdspccra; /* 0x228 Protocol Configuration A */ 495 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 496 u8 res_230[0x800-0x230]; 497 struct { 498 u32 gcr0; /* 0x800 General Control Register 0 */ 499 u32 gcr1; /* 0x804 General Control Register 1 */ 500 u32 gcr2; /* 0x808 General Control Register 2 */ 501 u32 sscr0; 502 u32 recr0; /* 0x810 Receive Equalization Control */ 503 u32 recr1; 504 u32 tecr0; /* 0x818 Transmit Equalization Control */ 505 u32 sscr1; 506 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 507 u8 res_824[0x83c-0x824]; 508 u32 tcsr3; 509 } lane[4]; /* Lane A, B, C, D */ 510 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 511 struct { 512 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 513 u8 res_1004[0x1040-0x1004]; 514 } pcie[3]; 515 u8 res_10c0[0x1800-0x10c0]; 516 struct { 517 u8 res_1800[0x1804-0x1800]; 518 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 519 u8 res_1808[0x180c-0x1808]; 520 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 521 } sgmii[4]; /* Lane A, B, C, D */ 522 u8 res_1840[0x1880-0x1840]; 523 struct { 524 u8 res_1880[0x1884-0x1880]; 525 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 526 u8 res_1888[0x188c-0x1888]; 527 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 528 } qsgmii[2]; /* Lane A, B */ 529 u8 res_18a0[0x1980-0x18a0]; 530 struct { 531 u8 res_1980[0x1984-0x1980]; 532 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 533 u8 res_1988[0x198c-0x1988]; 534 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 535 } xfi[2]; /* Lane A, B */ 536 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 537 }; 538 539 #define CCI400_CTRLORD_TERM_BARRIER 0x00000008 540 #define CCI400_CTRLORD_EN_BARRIER 0 541 #define CCI400_SHAORD_NON_SHAREABLE 0x00000002 542 #define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 543 #define CCI400_SNOOP_REQ_EN 0x00000001 544 545 /* CCI-400 registers */ 546 struct ccsr_cci400 { 547 u32 ctrl_ord; /* Control Override */ 548 u32 spec_ctrl; /* Speculation Control */ 549 u32 secure_access; /* Secure Access */ 550 u32 status; /* Status */ 551 u32 impr_err; /* Imprecise Error */ 552 u8 res_14[0x100 - 0x14]; 553 u32 pmcr; /* Performance Monitor Control */ 554 u8 res_104[0xfd0 - 0x104]; 555 u32 pid[8]; /* Peripheral ID */ 556 u32 cid[4]; /* Component ID */ 557 struct { 558 u32 snoop_ctrl; /* Snoop Control */ 559 u32 sha_ord; /* Shareable Override */ 560 u8 res_1008[0x1100 - 0x1008]; 561 u32 rc_qos_ord; /* read channel QoS Value Override */ 562 u32 wc_qos_ord; /* read channel QoS Value Override */ 563 u8 res_1108[0x110c - 0x1108]; 564 u32 qos_ctrl; /* QoS Control */ 565 u32 max_ot; /* Max OT */ 566 u8 res_1114[0x1130 - 0x1114]; 567 u32 target_lat; /* Target Latency */ 568 u32 latency_regu; /* Latency Regulation */ 569 u32 qos_range; /* QoS Range */ 570 u8 res_113c[0x2000 - 0x113c]; 571 } slave[5]; /* Slave Interface */ 572 u8 res_6000[0x9004 - 0x6000]; 573 u32 cycle_counter; /* Cycle counter */ 574 u32 count_ctrl; /* Count Control */ 575 u32 overflow_status; /* Overflow Flag Status */ 576 u8 res_9010[0xa000 - 0x9010]; 577 struct { 578 u32 event_select; /* Event Select */ 579 u32 event_count; /* Event Count */ 580 u32 counter_ctrl; /* Counter Control */ 581 u32 overflow_status; /* Overflow Flag Status */ 582 u8 res_a010[0xb000 - 0xa010]; 583 } pcounter[4]; /* Performance Counter */ 584 u8 res_e004[0x10000 - 0xe004]; 585 }; 586 587 /* MMU 500 */ 588 #define SMMU_SCR0 (SMMU_BASE + 0x0) 589 #define SMMU_SCR1 (SMMU_BASE + 0x4) 590 #define SMMU_SCR2 (SMMU_BASE + 0x8) 591 #define SMMU_SACR (SMMU_BASE + 0x10) 592 #define SMMU_IDR0 (SMMU_BASE + 0x20) 593 #define SMMU_IDR1 (SMMU_BASE + 0x24) 594 595 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 596 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 597 #define SMMU_NSACR (SMMU_BASE + 0x410) 598 599 #define SCR0_CLIENTPD_MASK 0x00000001 600 #define SCR0_USFCFG_MASK 0x00000400 601 602 uint get_svr(void); 603 604 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 605