1 /* 2 * Copyright 2013-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 8 #define __ARCH_FSL_LSCH2_IMMAP_H__ 9 10 #include <fsl_immap.h> 11 12 #define CONFIG_SYS_IMMR 0x01000000 13 #define CONFIG_SYS_DCSRBAR 0x20000000 14 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040) 16 17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 18 #define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) 19 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 20 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 21 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 22 #define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 23 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 24 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 25 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 26 #define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) 27 #define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) 28 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) 29 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 30 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 31 #define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 32 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 33 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 34 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 35 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 36 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 37 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 38 #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 39 #define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) 40 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 41 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 42 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 43 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 44 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 45 46 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 47 #define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 48 #define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ 49 CONFIG_SYS_BMAN_MEM_BASE) 50 #define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 51 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 52 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 53 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 54 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 55 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 56 CONFIG_SYS_BMAN_CENA_SIZE) 57 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 58 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 59 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 60 #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 61 #define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \ 62 CONFIG_SYS_QMAN_MEM_BASE) 63 #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 64 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 65 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 66 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 67 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 68 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 69 CONFIG_SYS_QMAN_CENA_SIZE) 70 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 71 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 72 73 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 74 75 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 76 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 77 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 78 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 79 80 #define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 81 82 #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 83 #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 84 85 #define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) 86 #define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) 87 #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) 88 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) 89 90 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 91 92 #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 93 94 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 95 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 96 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 97 /* LUT registers */ 98 #ifdef CONFIG_ARCH_LS1012A 99 #define PCIE_LUT_BASE 0xC0000 100 #else 101 #define PCIE_LUT_BASE 0x10000 102 #endif 103 #define PCIE_LUT_LCTRL0 0x7F8 104 #define PCIE_LUT_DBG 0x7FC 105 106 /* TZ Address Space Controller Definitions */ 107 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 108 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 109 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 110 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 111 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 112 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 113 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 114 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 115 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 116 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 117 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 118 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 119 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 120 121 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 122 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 123 #define TP_ITYP_TYPE_ARM 0x0 124 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 125 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 126 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 127 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 128 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 129 #define TY_ITYP_VER_A7 0x1 130 #define TY_ITYP_VER_A53 0x2 131 #define TY_ITYP_VER_A57 0x3 132 #define TY_ITYP_VER_A72 0x4 133 134 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 135 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 136 #define TP_INIT_PER_CLUSTER 4 137 138 /* 139 * Define default values for some CCSR macros to make header files cleaner* 140 * 141 * To completely disable CCSR relocation in a board header file, define 142 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 143 * to a value that is the same as CONFIG_SYS_CCSRBAR. 144 */ 145 146 #ifdef CONFIG_SYS_CCSRBAR_PHYS 147 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 148 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 149 #endif 150 151 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 152 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 153 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 154 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 155 #endif 156 157 #ifndef CONFIG_SYS_CCSRBAR 158 #define CONFIG_SYS_CCSRBAR 0x01000000 159 #endif 160 161 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 162 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 163 #endif 164 165 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 166 #define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 167 #endif 168 169 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 170 CONFIG_SYS_CCSRBAR_PHYS_LOW) 171 172 struct sys_info { 173 unsigned long freq_processor[CONFIG_MAX_CPUS]; 174 /* frequency of platform PLL */ 175 unsigned long freq_systembus; 176 unsigned long freq_ddrbus; 177 unsigned long freq_localbus; 178 unsigned long freq_sdhc; 179 #ifdef CONFIG_SYS_DPAA_FMAN 180 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 181 #endif 182 unsigned long freq_qman; 183 }; 184 185 #define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 186 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 187 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 188 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 189 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 190 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 191 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 192 193 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 194 #define CONFIG_SYS_FSL_FM1_ADDR \ 195 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 196 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 197 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 198 199 #define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull 200 #define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull 201 #define CONFIG_SYS_FSL_SEC_ADDR \ 202 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 203 #define CONFIG_SYS_FSL_JR0_ADDR \ 204 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) 205 206 /* Device Configuration and Pin Control */ 207 #define DCFG_DCSR_PORCR1 0x0 208 #define DCFG_DCSR_ECCCR2 0x524 209 #define DISABLE_PFE_ECC BIT(13) 210 211 struct ccsr_gur { 212 u32 porsr1; /* POR status 1 */ 213 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 214 u32 porsr2; /* POR status 2 */ 215 u8 res_008[0x20-0x8]; 216 u32 gpporcr1; /* General-purpose POR configuration */ 217 u32 gpporcr2; 218 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 219 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 220 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 221 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 222 u32 dcfg_fusesr; /* Fuse status register */ 223 u8 res_02c[0x70-0x2c]; 224 u32 devdisr; /* Device disable control */ 225 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 226 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 227 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 228 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 229 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 230 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 231 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 232 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 233 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 234 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 235 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 236 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 237 u32 devdisr2; /* Device disable control 2 */ 238 u32 devdisr3; /* Device disable control 3 */ 239 u32 devdisr4; /* Device disable control 4 */ 240 u32 devdisr5; /* Device disable control 5 */ 241 u32 devdisr6; /* Device disable control 6 */ 242 u32 devdisr7; /* Device disable control 7 */ 243 u8 res_08c[0x94-0x8c]; 244 u32 coredisru; /* uppper portion for support of 64 cores */ 245 u32 coredisrl; /* lower portion for support of 64 cores */ 246 u8 res_09c[0xa0-0x9c]; 247 u32 pvr; /* Processor version */ 248 u32 svr; /* System version */ 249 u32 mvr; /* Manufacturing version */ 250 u8 res_0ac[0xb0-0xac]; 251 u32 rstcr; /* Reset control */ 252 u32 rstrqpblsr; /* Reset request preboot loader status */ 253 u8 res_0b8[0xc0-0xb8]; 254 u32 rstrqmr1; /* Reset request mask */ 255 u8 res_0c4[0xc8-0xc4]; 256 u32 rstrqsr1; /* Reset request status */ 257 u8 res_0cc[0xd4-0xcc]; 258 u32 rstrqwdtmrl; /* Reset request WDT mask */ 259 u8 res_0d8[0xdc-0xd8]; 260 u32 rstrqwdtsrl; /* Reset request WDT status */ 261 u8 res_0e0[0xe4-0xe0]; 262 u32 brrl; /* Boot release */ 263 u8 res_0e8[0x100-0xe8]; 264 u32 rcwsr[16]; /* Reset control word status */ 265 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 266 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 267 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 268 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 269 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 270 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 271 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 272 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 273 #define RCW_SB_EN_REG_INDEX 7 274 #define RCW_SB_EN_MASK 0x00200000 275 276 u8 res_140[0x200-0x140]; 277 u32 scratchrw[4]; /* Scratch Read/Write */ 278 u8 res_210[0x300-0x210]; 279 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 280 u8 res_310[0x400-0x310]; 281 u32 crstsr[12]; 282 u8 res_430[0x500-0x430]; 283 284 /* PCI Express n Logical I/O Device Number register */ 285 u32 dcfg_ccsr_pex1liodnr; 286 u32 dcfg_ccsr_pex2liodnr; 287 u32 dcfg_ccsr_pex3liodnr; 288 u32 dcfg_ccsr_pex4liodnr; 289 /* RIO n Logical I/O Device Number register */ 290 u32 dcfg_ccsr_rio1liodnr; 291 u32 dcfg_ccsr_rio2liodnr; 292 u32 dcfg_ccsr_rio3liodnr; 293 u32 dcfg_ccsr_rio4liodnr; 294 /* USB Logical I/O Device Number register */ 295 u32 dcfg_ccsr_usb1liodnr; 296 u32 dcfg_ccsr_usb2liodnr; 297 u32 dcfg_ccsr_usb3liodnr; 298 u32 dcfg_ccsr_usb4liodnr; 299 /* SD/MMC Logical I/O Device Number register */ 300 u32 dcfg_ccsr_sdmmc1liodnr; 301 u32 dcfg_ccsr_sdmmc2liodnr; 302 u32 dcfg_ccsr_sdmmc3liodnr; 303 u32 dcfg_ccsr_sdmmc4liodnr; 304 /* RIO Message Unit Logical I/O Device Number register */ 305 u32 dcfg_ccsr_riomaintliodnr; 306 307 u8 res_544[0x550-0x544]; 308 u32 sataliodnr[4]; 309 u8 res_560[0x570-0x560]; 310 311 u32 dcfg_ccsr_misc1liodnr; 312 u32 dcfg_ccsr_misc2liodnr; 313 u32 dcfg_ccsr_misc3liodnr; 314 u32 dcfg_ccsr_misc4liodnr; 315 u32 dcfg_ccsr_dma1liodnr; 316 u32 dcfg_ccsr_dma2liodnr; 317 u32 dcfg_ccsr_dma3liodnr; 318 u32 dcfg_ccsr_dma4liodnr; 319 u32 dcfg_ccsr_spare1liodnr; 320 u32 dcfg_ccsr_spare2liodnr; 321 u32 dcfg_ccsr_spare3liodnr; 322 u32 dcfg_ccsr_spare4liodnr; 323 u8 res_5a0[0x600-0x5a0]; 324 u32 dcfg_ccsr_pblsr; 325 326 u32 pamubypenr; 327 u32 dmacr1; 328 329 u8 res_60c[0x610-0x60c]; 330 u32 dcfg_ccsr_gensr1; 331 u32 dcfg_ccsr_gensr2; 332 u32 dcfg_ccsr_gensr3; 333 u32 dcfg_ccsr_gensr4; 334 u32 dcfg_ccsr_gencr1; 335 u32 dcfg_ccsr_gencr2; 336 u32 dcfg_ccsr_gencr3; 337 u32 dcfg_ccsr_gencr4; 338 u32 dcfg_ccsr_gencr5; 339 u32 dcfg_ccsr_gencr6; 340 u32 dcfg_ccsr_gencr7; 341 u8 res_63c[0x658-0x63c]; 342 u32 dcfg_ccsr_cgensr1; 343 u32 dcfg_ccsr_cgensr0; 344 u8 res_660[0x678-0x660]; 345 u32 dcfg_ccsr_cgencr1; 346 347 u32 dcfg_ccsr_cgencr0; 348 u8 res_680[0x700-0x680]; 349 u32 dcfg_ccsr_sriopstecr; 350 u32 dcfg_ccsr_dcsrcr; 351 352 u8 res_708[0x740-0x708]; /* add more registers when needed */ 353 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 354 struct { 355 u32 upper; 356 u32 lower; 357 } tp_cluster[16]; 358 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 359 u32 dcfg_ccsr_qmbm_warmrst; 360 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 361 u32 dcfg_ccsr_reserved0; 362 u32 dcfg_ccsr_reserved1; 363 }; 364 365 #define SCFG_QSPI_CLKSEL 0x40100000 366 #define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 367 #define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 368 #define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 369 #define SCFG_USBPWRFAULT_INACTIVE 0x00000000 370 #define SCFG_USBPWRFAULT_SHARED 0x00000001 371 #define SCFG_USBPWRFAULT_DEDICATED 0x00000002 372 #define SCFG_USBPWRFAULT_USB3_SHIFT 4 373 #define SCFG_USBPWRFAULT_USB2_SHIFT 2 374 #define SCFG_USBPWRFAULT_USB1_SHIFT 0 375 376 #define SCFG_BASE 0x01570000 377 #define SCFG_USB3PRM1CR_USB1 0x070 378 #define SCFG_USB3PRM2CR_USB1 0x074 379 #define SCFG_USB3PRM1CR_USB2 0x07C 380 #define SCFG_USB3PRM2CR_USB2 0x080 381 #define SCFG_USB3PRM1CR_USB3 0x088 382 #define SCFG_USB3PRM2CR_USB3 0x08c 383 #define SCFG_USB_TXVREFTUNE 0x9 384 #define SCFG_USB_SQRXTUNE_MASK 0x7 385 #define SCFG_USB_PCSTXSWINGFULL 0x47 386 #define SCFG_USB_PHY1 0x084F0000 387 #define SCFG_USB_PHY2 0x08500000 388 #define SCFG_USB_PHY3 0x08510000 389 #define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 390 #define USB_PHY_RX_EQ_VAL_1 0x0000 391 #define USB_PHY_RX_EQ_VAL_2 0x0080 392 #define USB_PHY_RX_EQ_VAL_3 0x0380 393 #define USB_PHY_RX_EQ_VAL_4 0x0b80 394 395 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 396 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 397 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 398 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 399 400 /* RGMIIPCR bit definitions*/ 401 #define SCFG_RGMIIPCR_EN_AUTO BIT(3) 402 #define SCFG_RGMIIPCR_SETSP_1000M BIT(2) 403 #define SCFG_RGMIIPCR_SETSP_100M 0 404 #define SCFG_RGMIIPCR_SETSP_10M BIT(1) 405 #define SCFG_RGMIIPCR_SETFD BIT(0) 406 407 /* PFEASBCR bit definitions */ 408 #define SCFG_PFEASBCR_ARCACHE0 BIT(31) 409 #define SCFG_PFEASBCR_AWCACHE0 BIT(30) 410 #define SCFG_PFEASBCR_ARCACHE1 BIT(29) 411 #define SCFG_PFEASBCR_AWCACHE1 BIT(28) 412 #define SCFG_PFEASBCR_ARSNP BIT(27) 413 #define SCFG_PFEASBCR_AWSNP BIT(26) 414 415 /* WR_QoS1 PFE bit definitions */ 416 #define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) 417 #define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) 418 419 /* RD_QoS1 PFE bit definitions */ 420 #define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) 421 #define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) 422 423 /* Supplemental Configuration Unit */ 424 struct ccsr_scfg { 425 u8 res_000[0x100-0x000]; 426 u32 usb2_icid; 427 u32 usb3_icid; 428 u8 res_108[0x114-0x108]; 429 u32 dma_icid; 430 u32 sata_icid; 431 u32 usb1_icid; 432 u32 qe_icid; 433 u32 sdhc_icid; 434 u32 edma_icid; 435 u32 etr_icid; 436 u32 core_sft_rst[4]; 437 u8 res_140[0x158-0x140]; 438 u32 altcbar; 439 u32 qspi_cfg; 440 u8 res_160[0x164 - 0x160]; 441 u32 wr_qos1; 442 u32 wr_qos2; 443 u32 rd_qos1; 444 u32 rd_qos2; 445 u8 res_174[0x180 - 0x174]; 446 u32 dmamcr; 447 u8 res_184[0x188-0x184]; 448 u32 gic_align; 449 u32 debug_icid; 450 u8 res_190[0x1a4-0x190]; 451 u32 snpcnfgcr; 452 u8 res_1a8[0x1ac-0x1a8]; 453 u32 intpcr; 454 u8 res_1b0[0x204-0x1b0]; 455 u32 coresrencr; 456 u8 res_208[0x220-0x208]; 457 u32 rvbar0_0; 458 u32 rvbar0_1; 459 u32 rvbar1_0; 460 u32 rvbar1_1; 461 u32 rvbar2_0; 462 u32 rvbar2_1; 463 u32 rvbar3_0; 464 u32 rvbar3_1; 465 u32 lpmcsr; 466 u8 res_244[0x400-0x244]; 467 u32 qspidqscr; 468 u32 ecgtxcmcr; 469 u32 sdhciovselcr; 470 u32 rcwpmuxcr0; 471 u32 usbdrvvbus_selcr; 472 u32 usbpwrfault_selcr; 473 u32 usb_refclk_selcr1; 474 u32 usb_refclk_selcr2; 475 u32 usb_refclk_selcr3; 476 u8 res_424[0x434 - 0x424]; 477 u32 rgmiipcr; 478 u32 res_438; 479 u32 rgmiipsr; 480 u32 pfepfcssr1; 481 u32 pfeintencr1; 482 u32 pfepfcssr2; 483 u32 pfeintencr2; 484 u32 pfeerrcr; 485 u32 pfeeerrintencr; 486 u32 pfeasbcr; 487 u32 pfebsbcr; 488 u8 res_460[0x484 - 0x460]; 489 u32 mdioselcr; 490 u8 res_468[0x600 - 0x488]; 491 u32 scratchrw[4]; 492 u8 res_610[0x680-0x610]; 493 u32 corebcr; 494 u8 res_684[0x1000-0x684]; 495 u32 pex1msiir; 496 u32 pex1msir; 497 u8 res_1008[0x2000-0x1008]; 498 u32 pex2; 499 u32 pex2msir; 500 u8 res_2008[0x3000-0x2008]; 501 u32 pex3msiir; 502 u32 pex3msir; 503 }; 504 505 /* Clocking */ 506 struct ccsr_clk { 507 struct { 508 u32 clkcncsr; /* core cluster n clock control status */ 509 u8 res_004[0x0c]; 510 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 511 u8 res_014[0x0c]; 512 } clkcsr[4]; 513 u8 res_040[0x780]; /* 0x100 */ 514 struct { 515 u32 pllcngsr; 516 u8 res_804[0x1c]; 517 } pllcgsr[2]; 518 u8 res_840[0x1c0]; 519 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 520 u8 res_a04[0x1fc]; 521 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 522 u8 res_c04[0x1c]; 523 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 524 u8 res_c24[0x3dc]; 525 }; 526 527 /* System Counter */ 528 struct sctr_regs { 529 u32 cntcr; 530 u32 cntsr; 531 u32 cntcv1; 532 u32 cntcv2; 533 u32 resv1[4]; 534 u32 cntfid0; 535 u32 cntfid1; 536 u32 resv2[1002]; 537 u32 counterid[12]; 538 }; 539 540 #define SRDS_MAX_LANES 4 541 struct ccsr_serdes { 542 struct { 543 u32 rstctl; /* Reset Control Register */ 544 #define SRDS_RSTCTL_RST 0x80000000 545 #define SRDS_RSTCTL_RSTDONE 0x40000000 546 #define SRDS_RSTCTL_RSTERR 0x20000000 547 #define SRDS_RSTCTL_SWRST 0x10000000 548 #define SRDS_RSTCTL_SDEN 0x00000020 549 #define SRDS_RSTCTL_SDRST_B 0x00000040 550 #define SRDS_RSTCTL_PLLRST_B 0x00000080 551 u32 pllcr0; /* PLL Control Register 0 */ 552 #define SRDS_PLLCR0_POFF 0x80000000 553 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 554 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 555 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 556 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 557 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 558 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 559 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 560 #define SRDS_PLLCR0_PLL_LCK 0x00800000 561 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 562 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 563 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 564 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 565 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 566 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 567 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 568 u32 pllcr1; /* PLL Control Register 1 */ 569 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 570 u32 res_0c; /* 0x00c */ 571 u32 pllcr3; 572 u32 pllcr4; 573 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 574 u8 res_1c[0x20-0x1c]; 575 } bank[2]; 576 u8 res_40[0x90-0x40]; 577 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 578 u8 res_94[0xa0-0x94]; 579 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 580 u8 res_a4[0xb0-0xa4]; 581 u32 srdsgr0; /* 0xb0 General Register 0 */ 582 u8 res_b4[0x100-0xb4]; 583 struct { 584 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 585 u8 res_104[0x120-0x104]; 586 } lnpssr[4]; /* Lane A, B, C, D */ 587 u8 res_180[0x200-0x180]; 588 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 589 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 590 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 591 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 592 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 593 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 594 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 595 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 596 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 597 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 598 u32 srdspccra; /* 0x228 Protocol Configuration A */ 599 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 600 u8 res_230[0x800-0x230]; 601 struct { 602 u32 gcr0; /* 0x800 General Control Register 0 */ 603 u32 gcr1; /* 0x804 General Control Register 1 */ 604 u32 gcr2; /* 0x808 General Control Register 2 */ 605 u32 sscr0; 606 u32 recr0; /* 0x810 Receive Equalization Control */ 607 u32 recr1; 608 u32 tecr0; /* 0x818 Transmit Equalization Control */ 609 u32 sscr1; 610 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 611 u8 res_824[0x83c-0x824]; 612 u32 tcsr3; 613 } lane[4]; /* Lane A, B, C, D */ 614 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 615 struct { 616 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 617 u8 res_1004[0x1040-0x1004]; 618 } pcie[3]; 619 u8 res_10c0[0x1800-0x10c0]; 620 struct { 621 u8 res_1800[0x1804-0x1800]; 622 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 623 u8 res_1808[0x180c-0x1808]; 624 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 625 } sgmii[4]; /* Lane A, B, C, D */ 626 u8 res_1840[0x1880-0x1840]; 627 struct { 628 u8 res_1880[0x1884-0x1880]; 629 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 630 u8 res_1888[0x188c-0x1888]; 631 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 632 } qsgmii[2]; /* Lane A, B */ 633 u8 res_18a0[0x1980-0x18a0]; 634 struct { 635 u8 res_1980[0x1984-0x1980]; 636 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 637 u8 res_1988[0x198c-0x1988]; 638 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 639 } xfi[2]; /* Lane A, B */ 640 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 641 }; 642 643 struct ccsr_gpio { 644 u32 gpdir; 645 u32 gpodr; 646 u32 gpdat; 647 u32 gpier; 648 u32 gpimr; 649 u32 gpicr; 650 u32 gpibe; 651 }; 652 653 /* MMU 500 */ 654 #define SMMU_SCR0 (SMMU_BASE + 0x0) 655 #define SMMU_SCR1 (SMMU_BASE + 0x4) 656 #define SMMU_SCR2 (SMMU_BASE + 0x8) 657 #define SMMU_SACR (SMMU_BASE + 0x10) 658 #define SMMU_IDR0 (SMMU_BASE + 0x20) 659 #define SMMU_IDR1 (SMMU_BASE + 0x24) 660 661 #define SMMU_NSCR0 (SMMU_BASE + 0x400) 662 #define SMMU_NSCR2 (SMMU_BASE + 0x408) 663 #define SMMU_NSACR (SMMU_BASE + 0x410) 664 665 #define SCR0_CLIENTPD_MASK 0x00000001 666 #define SCR0_USFCFG_MASK 0x00000400 667 668 uint get_svr(void); 669 670 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 671