1 /*
2  * Copyright 2013-2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
8 #define __ARCH_FSL_LSCH2_IMMAP_H__
9 
10 #include <fsl_immap.h>
11 
12 #define CONFIG_SYS_IMMR				0x01000000
13 #define CONFIG_SYS_DCSRBAR			0x20000000
14 #define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR	(CONFIG_SYS_DCSRBAR + 0x02008040)
16 
17 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
18 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
19 #define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
20 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
21 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
22 #define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
23 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
24 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
25 #define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
26 #define CONFIG_SYS_FSL_FMAN_ADDR		(CONFIG_SYS_IMMR + 0x00a00000)
27 #define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
28 #define CONFIG_SYS_FSL_DCFG_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
29 #define CONFIG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
30 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
31 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
32 #define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
33 #define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
34 #define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR	(CONFIG_SYS_IMMR + 0x01f00000)
35 #define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR	(CONFIG_SYS_IMMR + 0x02000000)
36 #define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR	(CONFIG_SYS_IMMR + 0x02100000)
37 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
38 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
39 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
40 #define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
41 #define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
42 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
43 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
44 
45 #define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
46 
47 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
48 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
49 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
50 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011b0000)
51 
52 #define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
53 
54 #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
55 #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
56 
57 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
58 
59 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
60 
61 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
62 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
63 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
64 /* LUT registers */
65 #define PCIE_LUT_BASE				0x10000
66 #define PCIE_LUT_LCTRL0				0x7F8
67 #define PCIE_LUT_DBG				0x7FC
68 
69 /* TZ Address Space Controller Definitions */
70 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
71 #define TZASC2_BASE			0x01110000	/* as per CCSR map. */
72 #define TZASC3_BASE			0x01120000	/* as per CCSR map. */
73 #define TZASC4_BASE			0x01130000	/* as per CCSR map. */
74 #define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
75 #define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
76 #define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
77 #define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
78 #define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
79 #define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
80 #define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
81 #define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
82 #define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
83 
84 #define TP_ITYP_AV              0x00000001      /* Initiator available */
85 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
86 #define TP_ITYP_TYPE_ARM        0x0
87 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
88 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
89 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
90 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
91 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
92 #define TY_ITYP_VER_A7          0x1
93 #define TY_ITYP_VER_A53         0x2
94 #define TY_ITYP_VER_A57         0x3
95 
96 #define TP_CLUSTER_EOC		0xc0000000      /* end of clusters */
97 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
98 #define TP_INIT_PER_CLUSTER     4
99 
100 /*
101  * Define default values for some CCSR macros to make header files cleaner*
102  *
103  * To completely disable CCSR relocation in a board header file, define
104  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
105  * to a value that is the same as CONFIG_SYS_CCSRBAR.
106  */
107 
108 #ifdef CONFIG_SYS_CCSRBAR_PHYS
109 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
110 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
111 #endif
112 
113 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
114 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
115 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
116 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
117 #endif
118 
119 #ifndef CONFIG_SYS_CCSRBAR
120 #define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
121 #endif
122 
123 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
124 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
125 #endif
126 
127 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
128 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
129 #endif
130 
131 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
132 				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
133 
134 struct sys_info {
135 	unsigned long freq_processor[CONFIG_MAX_CPUS];
136 	unsigned long freq_systembus;
137 	unsigned long freq_ddrbus;
138 	unsigned long freq_localbus;
139 	unsigned long freq_sdhc;
140 #ifdef CONFIG_SYS_DPAA_FMAN
141 	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
142 #endif
143 	unsigned long freq_qman;
144 };
145 
146 #define CONFIG_SYS_FSL_FM1_OFFSET		0xa00000
147 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0xa88000
148 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0xa89000
149 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0xa8a000
150 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0xa8b000
151 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0xa8c000
152 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0xa8d000
153 
154 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
155 #define CONFIG_SYS_FSL_FM1_ADDR			\
156 		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
157 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
158 		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
159 
160 /* Device Configuration and Pin Control */
161 struct ccsr_gur {
162 	u32     porsr1;         /* POR status 1 */
163 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK	0xFF800000
164 	u32     porsr2;         /* POR status 2 */
165 	u8      res_008[0x20-0x8];
166 	u32     gpporcr1;       /* General-purpose POR configuration */
167 	u32	gpporcr2;
168 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT	25
169 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK	0x1F
170 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT	20
171 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK	0x1F
172 	u32     dcfg_fusesr;    /* Fuse status register */
173 	u8      res_02c[0x70-0x2c];
174 	u32     devdisr;        /* Device disable control */
175 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1	0x80000000
176 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2	0x40000000
177 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3	0x20000000
178 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4	0x10000000
179 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5	0x08000000
180 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6	0x04000000
181 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9	0x00800000
182 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10	0x00400000
183 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1	0x00800000
184 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
185 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
186 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
187 	u32     devdisr2;       /* Device disable control 2 */
188 	u32     devdisr3;       /* Device disable control 3 */
189 	u32     devdisr4;       /* Device disable control 4 */
190 	u32     devdisr5;       /* Device disable control 5 */
191 	u32     devdisr6;       /* Device disable control 6 */
192 	u32     devdisr7;       /* Device disable control 7 */
193 	u8      res_08c[0x94-0x8c];
194 	u32     coredisru;      /* uppper portion for support of 64 cores */
195 	u32     coredisrl;      /* lower portion for support of 64 cores */
196 	u8      res_09c[0xa0-0x9c];
197 	u32     pvr;            /* Processor version */
198 	u32     svr;            /* System version */
199 	u32     mvr;            /* Manufacturing version */
200 	u8	res_0ac[0xb0-0xac];
201 	u32	rstcr;		/* Reset control */
202 	u32	rstrqpblsr;	/* Reset request preboot loader status */
203 	u8	res_0b8[0xc0-0xb8];
204 	u32	rstrqmr1;	/* Reset request mask */
205 	u8	res_0c4[0xc8-0xc4];
206 	u32	rstrqsr1;	/* Reset request status */
207 	u8	res_0cc[0xd4-0xcc];
208 	u32	rstrqwdtmrl;	/* Reset request WDT mask */
209 	u8	res_0d8[0xdc-0xd8];
210 	u32	rstrqwdtsrl;	/* Reset request WDT status */
211 	u8	res_0e0[0xe4-0xe0];
212 	u32	brrl;		/* Boot release */
213 	u8      res_0e8[0x100-0xe8];
214 	u32     rcwsr[16];      /* Reset control word status */
215 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT	25
216 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK	0x1f
217 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT	16
218 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK	0x3f
219 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK	0xffff0000
220 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT	16
221 #define RCW_SB_EN_REG_INDEX	7
222 #define RCW_SB_EN_MASK		0x00200000
223 
224 	u8      res_140[0x200-0x140];
225 	u32     scratchrw[4];  /* Scratch Read/Write */
226 	u8      res_210[0x300-0x210];
227 	u32     scratchw1r[4];  /* Scratch Read (Write once) */
228 	u8      res_310[0x400-0x310];
229 	u32	crstsr[12];
230 	u8	res_430[0x500-0x430];
231 
232 	/* PCI Express n Logical I/O Device Number register */
233 	u32 dcfg_ccsr_pex1liodnr;
234 	u32 dcfg_ccsr_pex2liodnr;
235 	u32 dcfg_ccsr_pex3liodnr;
236 	u32 dcfg_ccsr_pex4liodnr;
237 	/* RIO n Logical I/O Device Number register */
238 	u32 dcfg_ccsr_rio1liodnr;
239 	u32 dcfg_ccsr_rio2liodnr;
240 	u32 dcfg_ccsr_rio3liodnr;
241 	u32 dcfg_ccsr_rio4liodnr;
242 	/* USB Logical I/O Device Number register */
243 	u32 dcfg_ccsr_usb1liodnr;
244 	u32 dcfg_ccsr_usb2liodnr;
245 	u32 dcfg_ccsr_usb3liodnr;
246 	u32 dcfg_ccsr_usb4liodnr;
247 	/* SD/MMC Logical I/O Device Number register */
248 	u32 dcfg_ccsr_sdmmc1liodnr;
249 	u32 dcfg_ccsr_sdmmc2liodnr;
250 	u32 dcfg_ccsr_sdmmc3liodnr;
251 	u32 dcfg_ccsr_sdmmc4liodnr;
252 	/* RIO Message Unit Logical I/O Device Number register */
253 	u32 dcfg_ccsr_riomaintliodnr;
254 
255 	u8      res_544[0x550-0x544];
256 	u32	sataliodnr[4];
257 	u8	res_560[0x570-0x560];
258 
259 	u32 dcfg_ccsr_misc1liodnr;
260 	u32 dcfg_ccsr_misc2liodnr;
261 	u32 dcfg_ccsr_misc3liodnr;
262 	u32 dcfg_ccsr_misc4liodnr;
263 	u32 dcfg_ccsr_dma1liodnr;
264 	u32 dcfg_ccsr_dma2liodnr;
265 	u32 dcfg_ccsr_dma3liodnr;
266 	u32 dcfg_ccsr_dma4liodnr;
267 	u32 dcfg_ccsr_spare1liodnr;
268 	u32 dcfg_ccsr_spare2liodnr;
269 	u32 dcfg_ccsr_spare3liodnr;
270 	u32 dcfg_ccsr_spare4liodnr;
271 	u8	res_5a0[0x600-0x5a0];
272 	u32 dcfg_ccsr_pblsr;
273 
274 	u32	pamubypenr;
275 	u32	dmacr1;
276 
277 	u8	res_60c[0x610-0x60c];
278 	u32 dcfg_ccsr_gensr1;
279 	u32 dcfg_ccsr_gensr2;
280 	u32 dcfg_ccsr_gensr3;
281 	u32 dcfg_ccsr_gensr4;
282 	u32 dcfg_ccsr_gencr1;
283 	u32 dcfg_ccsr_gencr2;
284 	u32 dcfg_ccsr_gencr3;
285 	u32 dcfg_ccsr_gencr4;
286 	u32 dcfg_ccsr_gencr5;
287 	u32 dcfg_ccsr_gencr6;
288 	u32 dcfg_ccsr_gencr7;
289 	u8	res_63c[0x658-0x63c];
290 	u32 dcfg_ccsr_cgensr1;
291 	u32 dcfg_ccsr_cgensr0;
292 	u8	res_660[0x678-0x660];
293 	u32 dcfg_ccsr_cgencr1;
294 
295 	u32 dcfg_ccsr_cgencr0;
296 	u8	res_680[0x700-0x680];
297 	u32 dcfg_ccsr_sriopstecr;
298 	u32 dcfg_ccsr_dcsrcr;
299 
300 	u8      res_708[0x740-0x708];   /* add more registers when needed */
301 	u32     tp_ityp[64];    /* Topology Initiator Type Register */
302 	struct {
303 		u32     upper;
304 		u32     lower;
305 	} tp_cluster[16];
306 	u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
307 	u32 dcfg_ccsr_qmbm_warmrst;
308 	u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
309 	u32 dcfg_ccsr_reserved0;
310 	u32 dcfg_ccsr_reserved1;
311 };
312 
313 #define SCFG_QSPI_CLKSEL		0x40100000
314 #define SCFG_USBDRVVBUS_SELCR_USB1	0x00000000
315 #define SCFG_USBDRVVBUS_SELCR_USB2	0x00000001
316 #define SCFG_USBDRVVBUS_SELCR_USB3	0x00000002
317 #define SCFG_USBPWRFAULT_INACTIVE	0x00000000
318 #define SCFG_USBPWRFAULT_SHARED		0x00000001
319 #define SCFG_USBPWRFAULT_DEDICATED	0x00000002
320 #define SCFG_USBPWRFAULT_USB3_SHIFT	4
321 #define SCFG_USBPWRFAULT_USB2_SHIFT	2
322 #define SCFG_USBPWRFAULT_USB1_SHIFT	0
323 
324 #define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
325 #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
326 
327 /* Supplemental Configuration Unit */
328 struct ccsr_scfg {
329 	u8 res_000[0x100-0x000];
330 	u32 usb2_icid;
331 	u32 usb3_icid;
332 	u8 res_108[0x114-0x108];
333 	u32 dma_icid;
334 	u32 sata_icid;
335 	u32 usb1_icid;
336 	u32 qe_icid;
337 	u32 sdhc_icid;
338 	u32 edma_icid;
339 	u32 etr_icid;
340 	u32 core_sft_rst[4];
341 	u8 res_140[0x158-0x140];
342 	u32 altcbar;
343 	u32 qspi_cfg;
344 	u8 res_160[0x180-0x160];
345 	u32 dmamcr;
346 	u8 res_184[0x18c-0x184];
347 	u32 debug_icid;
348 	u8 res_190[0x1a4-0x190];
349 	u32 snpcnfgcr;
350 	u8 res_1a8[0x1ac-0x1a8];
351 	u32 intpcr;
352 	u8 res_1b0[0x204-0x1b0];
353 	u32 coresrencr;
354 	u8 res_208[0x220-0x208];
355 	u32 rvbar0_0;
356 	u32 rvbar0_1;
357 	u32 rvbar1_0;
358 	u32 rvbar1_1;
359 	u32 rvbar2_0;
360 	u32 rvbar2_1;
361 	u32 rvbar3_0;
362 	u32 rvbar3_1;
363 	u32 lpmcsr;
364 	u8 res_244[0x400-0x244];
365 	u32 qspidqscr;
366 	u32 ecgtxcmcr;
367 	u32 sdhciovselcr;
368 	u32 rcwpmuxcr0;
369 	u32 usbdrvvbus_selcr;
370 	u32 usbpwrfault_selcr;
371 	u32 usb_refclk_selcr1;
372 	u32 usb_refclk_selcr2;
373 	u32 usb_refclk_selcr3;
374 	u8 res_424[0x600-0x424];
375 	u32 scratchrw[4];
376 	u8 res_610[0x680-0x610];
377 	u32 corebcr;
378 	u8 res_684[0x1000-0x684];
379 	u32 pex1msiir;
380 	u32 pex1msir;
381 	u8 res_1008[0x2000-0x1008];
382 	u32 pex2;
383 	u32 pex2msir;
384 	u8 res_2008[0x3000-0x2008];
385 	u32 pex3msiir;
386 	u32 pex3msir;
387 };
388 
389 /* Clocking */
390 struct ccsr_clk {
391 	struct {
392 		u32 clkcncsr;	/* core cluster n clock control status */
393 		u8  res_004[0x0c];
394 		u32 clkcghwacsr; /* Clock generator n hardware accelerator */
395 		u8  res_014[0x0c];
396 	} clkcsr[4];
397 	u8	res_040[0x780]; /* 0x100 */
398 	struct {
399 		u32 pllcngsr;
400 		u8 res_804[0x1c];
401 	} pllcgsr[2];
402 	u8	res_840[0x1c0];
403 	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
404 	u8	res_a04[0x1fc];
405 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
406 	u8	res_c04[0x1c];
407 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
408 	u8	res_c24[0x3dc];
409 };
410 
411 /* System Counter */
412 struct sctr_regs {
413 	u32 cntcr;
414 	u32 cntsr;
415 	u32 cntcv1;
416 	u32 cntcv2;
417 	u32 resv1[4];
418 	u32 cntfid0;
419 	u32 cntfid1;
420 	u32 resv2[1002];
421 	u32 counterid[12];
422 };
423 
424 #define SRDS_MAX_LANES		4
425 struct ccsr_serdes {
426 	struct {
427 		u32	rstctl;	/* Reset Control Register */
428 #define SRDS_RSTCTL_RST		0x80000000
429 #define SRDS_RSTCTL_RSTDONE	0x40000000
430 #define SRDS_RSTCTL_RSTERR	0x20000000
431 #define SRDS_RSTCTL_SWRST	0x10000000
432 #define SRDS_RSTCTL_SDEN	0x00000020
433 #define SRDS_RSTCTL_SDRST_B	0x00000040
434 #define SRDS_RSTCTL_PLLRST_B	0x00000080
435 		u32	pllcr0; /* PLL Control Register 0 */
436 #define SRDS_PLLCR0_POFF		0x80000000
437 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
438 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
439 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
440 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
441 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
442 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
443 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
444 #define SRDS_PLLCR0_PLL_LCK		0x00800000
445 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
446 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
447 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
448 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
449 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
450 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
451 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
452 		u32	pllcr1; /* PLL Control Register 1 */
453 #define SRDS_PLLCR1_PLL_BWSEL	0x08000000
454 		u32	res_0c;	/* 0x00c */
455 		u32	pllcr3;
456 		u32	pllcr4;
457 		u32	pllcr5; /* 0x018 SerDes PLL1 Control 5 */
458 		u8	res_1c[0x20-0x1c];
459 	} bank[2];
460 	u8	res_40[0x90-0x40];
461 	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
462 	u8	res_94[0xa0-0x94];
463 	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
464 	u8	res_a4[0xb0-0xa4];
465 	u32	srdsgr0;	/* 0xb0 General Register 0 */
466 	u8	res_b4[0x100-0xb4];
467 	struct {
468 		u32	lnpssr0;	/* 0x100, 0x120, 0x140, 0x160 */
469 		u8	res_104[0x120-0x104];
470 	} lnpssr[4];	/* Lane A, B, C, D */
471 	u8	res_180[0x200-0x180];
472 	u32	srdspccr0;	/* 0x200 Protocol Configuration 0 */
473 	u32	srdspccr1;	/* 0x204 Protocol Configuration 1 */
474 	u32	srdspccr2;	/* 0x208 Protocol Configuration 2 */
475 	u32	srdspccr3;	/* 0x20c Protocol Configuration 3 */
476 	u32	srdspccr4;	/* 0x210 Protocol Configuration 4 */
477 	u32	srdspccr5;	/* 0x214 Protocol Configuration 5 */
478 	u32	srdspccr6;	/* 0x218 Protocol Configuration 6 */
479 	u32	srdspccr7;	/* 0x21c Protocol Configuration 7 */
480 	u32	srdspccr8;	/* 0x220 Protocol Configuration 8 */
481 	u32	srdspccr9;	/* 0x224 Protocol Configuration 9 */
482 	u32	srdspccra;	/* 0x228 Protocol Configuration A */
483 	u32	srdspccrb;	/* 0x22c Protocol Configuration B */
484 	u8	res_230[0x800-0x230];
485 	struct {
486 		u32	gcr0;	/* 0x800 General Control Register 0 */
487 		u32	gcr1;	/* 0x804 General Control Register 1 */
488 		u32	gcr2;	/* 0x808 General Control Register 2 */
489 		u32	sscr0;
490 		u32	recr0;	/* 0x810 Receive Equalization Control */
491 		u32	recr1;
492 		u32	tecr0;	/* 0x818 Transmit Equalization Control */
493 		u32	sscr1;
494 		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
495 		u8	res_824[0x83c-0x824];
496 		u32	tcsr3;
497 	} lane[4];	/* Lane A, B, C, D */
498 	u8	res_900[0x1000-0x900];	/* from 0x900 to 0xfff */
499 	struct {
500 		u32	srdspexcr0;	/* 0x1000, 0x1040, 0x1080 */
501 		u8	res_1004[0x1040-0x1004];
502 	} pcie[3];
503 	u8	res_10c0[0x1800-0x10c0];
504 	struct {
505 		u8	res_1800[0x1804-0x1800];
506 		u32	srdssgmiicr1;	/* 0x1804 SGMII Protocol Control 1 */
507 		u8	res_1808[0x180c-0x1808];
508 		u32	srdssgmiicr3;	/* 0x180c SGMII Protocol Control 3 */
509 	} sgmii[4];	/* Lane A, B, C, D */
510 	u8	res_1840[0x1880-0x1840];
511 	struct {
512 		u8	res_1880[0x1884-0x1880];
513 		u32	srdsqsgmiicr1;	/* 0x1884 QSGMII Protocol Control 1 */
514 		u8	res_1888[0x188c-0x1888];
515 		u32	srdsqsgmiicr3;	/* 0x188c QSGMII Protocol Control 3 */
516 	} qsgmii[2];	/* Lane A, B */
517 	u8	res_18a0[0x1980-0x18a0];
518 	struct {
519 		u8	res_1980[0x1984-0x1980];
520 		u32	srdsxficr1;	/* 0x1984 XFI Protocol Control 1 */
521 		u8	res_1988[0x198c-0x1988];
522 		u32	srdsxficr3;	/* 0x198c XFI Protocol Control 3 */
523 	} xfi[2];	/* Lane A, B */
524 	u8	res_19a0[0x2000-0x19a0];	/* from 0x19a0 to 0x1fff */
525 };
526 
527 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
528 #define CCI400_CTRLORD_EN_BARRIER	0
529 #define CCI400_SHAORD_NON_SHAREABLE	0x00000002
530 #define CCI400_DVM_MESSAGE_REQ_EN	0x00000002
531 #define CCI400_SNOOP_REQ_EN		0x00000001
532 
533 /* CCI-400 registers */
534 struct ccsr_cci400 {
535 	u32 ctrl_ord;			/* Control Override */
536 	u32 spec_ctrl;			/* Speculation Control */
537 	u32 secure_access;		/* Secure Access */
538 	u32 status;			/* Status */
539 	u32 impr_err;			/* Imprecise Error */
540 	u8 res_14[0x100 - 0x14];
541 	u32 pmcr;			/* Performance Monitor Control */
542 	u8 res_104[0xfd0 - 0x104];
543 	u32 pid[8];			/* Peripheral ID */
544 	u32 cid[4];			/* Component ID */
545 	struct {
546 		u32 snoop_ctrl;		/* Snoop Control */
547 		u32 sha_ord;		/* Shareable Override */
548 		u8 res_1008[0x1100 - 0x1008];
549 		u32 rc_qos_ord;		/* read channel QoS Value Override */
550 		u32 wc_qos_ord;		/* read channel QoS Value Override */
551 		u8 res_1108[0x110c - 0x1108];
552 		u32 qos_ctrl;		/* QoS Control */
553 		u32 max_ot;		/* Max OT */
554 		u8 res_1114[0x1130 - 0x1114];
555 		u32 target_lat;		/* Target Latency */
556 		u32 latency_regu;	/* Latency Regulation */
557 		u32 qos_range;		/* QoS Range */
558 		u8 res_113c[0x2000 - 0x113c];
559 	} slave[5];			/* Slave Interface */
560 	u8 res_6000[0x9004 - 0x6000];
561 	u32 cycle_counter;		/* Cycle counter */
562 	u32 count_ctrl;			/* Count Control */
563 	u32 overflow_status;		/* Overflow Flag Status */
564 	u8 res_9010[0xa000 - 0x9010];
565 	struct {
566 		u32 event_select;	/* Event Select */
567 		u32 event_count;	/* Event Count */
568 		u32 counter_ctrl;	/* Counter Control */
569 		u32 overflow_status;	/* Overflow Flag Status */
570 		u8 res_a010[0xb000 - 0xa010];
571 	} pcounter[4];			/* Performance Counter */
572 	u8 res_e004[0x10000 - 0xe004];
573 };
574 
575 /* MMU 500 */
576 #define SMMU_SCR0			(SMMU_BASE + 0x0)
577 #define SMMU_SCR1			(SMMU_BASE + 0x4)
578 #define SMMU_SCR2			(SMMU_BASE + 0x8)
579 #define SMMU_SACR			(SMMU_BASE + 0x10)
580 #define SMMU_IDR0			(SMMU_BASE + 0x20)
581 #define SMMU_IDR1			(SMMU_BASE + 0x24)
582 
583 #define SMMU_NSCR0			(SMMU_BASE + 0x400)
584 #define SMMU_NSCR2			(SMMU_BASE + 0x408)
585 #define SMMU_NSACR			(SMMU_BASE + 0x410)
586 
587 #define SCR0_CLIENTPD_MASK		0x00000001
588 #define SCR0_USFCFG_MASK		0x00000400
589 
590 #endif	/* __ARCH_FSL_LSCH2_IMMAP_H__*/
591