1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __FSL_SERDES_H__ 8 #define __FSL_SERDES_H__ 9 10 #include <config.h> 11 12 #ifdef CONFIG_FSL_LSCH3 13 enum srds_prtcl { 14 /* 15 * Nobody will check whether the device 'NONE' has been configured, 16 * So use it to indicate if the serdes_prtcl_map has been initialized. 17 */ 18 NONE = 0, 19 PCIE1, 20 PCIE2, 21 PCIE3, 22 PCIE4, 23 SATA1, 24 SATA2, 25 XAUI1, 26 XAUI2, 27 XFI1, 28 XFI2, 29 XFI3, 30 XFI4, 31 XFI5, 32 XFI6, 33 XFI7, 34 XFI8, 35 SGMII1, 36 SGMII2, 37 SGMII3, 38 SGMII4, 39 SGMII5, 40 SGMII6, 41 SGMII7, 42 SGMII8, 43 SGMII9, 44 SGMII10, 45 SGMII11, 46 SGMII12, 47 SGMII13, 48 SGMII14, 49 SGMII15, 50 SGMII16, 51 QSGMII_A, 52 QSGMII_B, 53 QSGMII_C, 54 QSGMII_D, 55 SERDES_PRCTL_COUNT 56 }; 57 58 enum srds { 59 FSL_SRDS_1 = 0, 60 FSL_SRDS_2 = 1, 61 }; 62 #elif defined(CONFIG_FSL_LSCH2) 63 enum srds_prtcl { 64 /* 65 * Nobody will check whether the device 'NONE' has been configured, 66 * So use it to indicate if the serdes_prtcl_map has been initialized. 67 */ 68 NONE = 0, 69 PCIE1, 70 PCIE2, 71 PCIE3, 72 PCIE4, 73 SATA1, 74 SATA2, 75 SRIO1, 76 SRIO2, 77 SGMII_FM1_DTSEC1, 78 SGMII_FM1_DTSEC2, 79 SGMII_FM1_DTSEC3, 80 SGMII_FM1_DTSEC4, 81 SGMII_FM1_DTSEC5, 82 SGMII_FM1_DTSEC6, 83 SGMII_FM1_DTSEC9, 84 SGMII_FM1_DTSEC10, 85 SGMII_FM2_DTSEC1, 86 SGMII_FM2_DTSEC2, 87 SGMII_FM2_DTSEC3, 88 SGMII_FM2_DTSEC4, 89 SGMII_FM2_DTSEC5, 90 SGMII_FM2_DTSEC6, 91 SGMII_FM2_DTSEC9, 92 SGMII_FM2_DTSEC10, 93 SGMII_TSEC1, 94 SGMII_TSEC2, 95 SGMII_TSEC3, 96 SGMII_TSEC4, 97 XAUI_FM1, 98 XAUI_FM2, 99 AURORA, 100 CPRI1, 101 CPRI2, 102 CPRI3, 103 CPRI4, 104 CPRI5, 105 CPRI6, 106 CPRI7, 107 CPRI8, 108 XAUI_FM1_MAC9, 109 XAUI_FM1_MAC10, 110 XAUI_FM2_MAC9, 111 XAUI_FM2_MAC10, 112 HIGIG_FM1_MAC9, 113 HIGIG_FM1_MAC10, 114 HIGIG_FM2_MAC9, 115 HIGIG_FM2_MAC10, 116 QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */ 117 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ 118 QSGMII_FM2_A, 119 QSGMII_FM2_B, 120 XFI_FM1_MAC1, 121 XFI_FM1_MAC2, 122 XFI_FM1_MAC9, 123 XFI_FM1_MAC10, 124 XFI_FM2_MAC9, 125 XFI_FM2_MAC10, 126 INTERLAKEN, 127 QSGMII_SW1_A, /* Indicates ports on L2 Switch */ 128 QSGMII_SW1_B, 129 SGMII_2500_FM1_DTSEC1, 130 SGMII_2500_FM1_DTSEC2, 131 SGMII_2500_FM1_DTSEC3, 132 SGMII_2500_FM1_DTSEC4, 133 SGMII_2500_FM1_DTSEC5, 134 SGMII_2500_FM1_DTSEC6, 135 SGMII_2500_FM1_DTSEC9, 136 SGMII_2500_FM1_DTSEC10, 137 SGMII_2500_FM2_DTSEC1, 138 SGMII_2500_FM2_DTSEC2, 139 SGMII_2500_FM2_DTSEC3, 140 SGMII_2500_FM2_DTSEC4, 141 SGMII_2500_FM2_DTSEC5, 142 SGMII_2500_FM2_DTSEC6, 143 SGMII_2500_FM2_DTSEC9, 144 SGMII_2500_FM2_DTSEC10, 145 TX_CLK, 146 SERDES_PRCTL_COUNT 147 }; 148 149 enum srds { 150 FSL_SRDS_1 = 0, 151 FSL_SRDS_2 = 1, 152 }; 153 154 #endif 155 156 int is_serdes_configured(enum srds_prtcl device); 157 void fsl_serdes_init(void); 158 int serdes_get_first_lane(u32 sd, enum srds_prtcl device); 159 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); 160 int is_serdes_prtcl_valid(int serdes, u32 prtcl); 161 int serdes_get_number(int serdes, int cfg); 162 void fsl_rgmii_init(void); 163 164 #ifdef CONFIG_FSL_LSCH2 165 const char *serdes_clock_to_string(u32 clock); 166 int get_serdes_protocol(void); 167 #endif 168 #ifdef CONFIG_SYS_HAS_SERDES 169 /* Get the volt of SVDD in unit mV */ 170 int get_serdes_volt(void); 171 /* Set the volt of SVDD in unit mV */ 172 int set_serdes_volt(int svdd); 173 /* The target volt of SVDD in unit mV */ 174 int setup_serdes_volt(u32 svdd); 175 #endif 176 177 #endif /* __FSL_SERDES_H__ */ 178