1 /*
2  * Copyright 2014-2015, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
9 
10 static struct cpu_type cpu_type_list[] = {
11 	CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
12 	CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
13 	CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
14 	CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
15 	CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
16 	CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
17 	CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
18 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
19 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
20 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
21 	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
22 	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
23 	CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
24 };
25 
26 #ifndef CONFIG_SYS_DCACHE_OFF
27 
28 #ifdef CONFIG_FSL_LSCH3
29 #define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
30 #define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
31 #define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
32 #define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
33 #define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
34 #define CONFIG_SYS_FSL_IFC_SIZE1	0x10000000
35 #define CONFIG_SYS_FSL_IFC_SIZE1_1	0x400000
36 #define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
37 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
38 #define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
39 #define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
40 #define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
41 #define CONFIG_SYS_FSL_IFC_SIZE2	0x100000000
42 #define CONFIG_SYS_FSL_DCSR_BASE	0x700000000
43 #define CONFIG_SYS_FSL_DCSR_SIZE	0x40000000
44 #define CONFIG_SYS_FSL_MC_BASE		0x80c000000
45 #define CONFIG_SYS_FSL_MC_SIZE		0x4000000
46 #define CONFIG_SYS_FSL_NI_BASE		0x810000000
47 #define CONFIG_SYS_FSL_NI_SIZE		0x8000000
48 #define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
49 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
50 #define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
51 #define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
52 #define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
53 #define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
54 #define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
55 #define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
56 #define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
57 #define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
58 #define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
59 #define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
60 #define CONFIG_SYS_FSL_PEBUF_SIZE	0x400000000
61 #define CONFIG_SYS_FSL_DRAM_BASE2	0x8080000000
62 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x7F80000000
63 #elif defined(CONFIG_FSL_LSCH2)
64 #define CONFIG_SYS_FSL_BOOTROM_BASE	0x0
65 #define CONFIG_SYS_FSL_BOOTROM_SIZE	0x1000000
66 #define CONFIG_SYS_FSL_CCSR_BASE	0x1000000
67 #define CONFIG_SYS_FSL_CCSR_SIZE	0xf000000
68 #define CONFIG_SYS_FSL_DCSR_BASE	0x20000000
69 #define CONFIG_SYS_FSL_DCSR_SIZE	0x4000000
70 #define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
71 #define CONFIG_SYS_FSL_QSPI_SIZE	0x20000000
72 #define CONFIG_SYS_FSL_IFC_BASE		0x60000000
73 #define CONFIG_SYS_FSL_IFC_SIZE		0x20000000
74 #define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
75 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
76 #define CONFIG_SYS_FSL_QBMAN_BASE	0x500000000
77 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
78 #define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
79 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
80 #define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
81 #define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
82 #define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
83 #define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
84 #define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
85 #endif
86 
87 #define EARLY_PGTABLE_SIZE 0x5000
88 static struct mm_region early_map[] = {
89 #ifdef CONFIG_FSL_LSCH3
90 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
91 	  CONFIG_SYS_FSL_CCSR_SIZE,
92 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
93 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
94 	},
95 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
96 	  SYS_FSL_OCRAM_SPACE_SIZE,
97 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
98 	},
99 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
100 	  CONFIG_SYS_FSL_QSPI_SIZE1,
101 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
102 	/* For IFC Region #1, only the first 4MB is cache-enabled */
103 	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
104 	  CONFIG_SYS_FSL_IFC_SIZE1_1,
105 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
106 	},
107 	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
108 	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
109 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
110 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
111 	},
112 	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
113 	  CONFIG_SYS_FSL_IFC_SIZE1,
114 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
115 	},
116 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
117 	  CONFIG_SYS_FSL_DRAM_SIZE1,
118 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
119 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
120 #else	/* Start with nGnRnE and PXN and UXN to prevent speculative access */
121 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
122 #endif
123 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
124 	},
125 	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
126 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
127 	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
128 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
129 	},
130 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
131 	  CONFIG_SYS_FSL_DCSR_SIZE,
132 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
133 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
134 	},
135 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
136 	  CONFIG_SYS_FSL_DRAM_SIZE2,
137 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
138 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
139 	},
140 #elif defined(CONFIG_FSL_LSCH2)
141 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
142 	  CONFIG_SYS_FSL_CCSR_SIZE,
143 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
144 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
145 	},
146 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
147 	  SYS_FSL_OCRAM_SPACE_SIZE,
148 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
149 	},
150 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
151 	  CONFIG_SYS_FSL_DCSR_SIZE,
152 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
153 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
154 	},
155 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
156 	  CONFIG_SYS_FSL_QSPI_SIZE,
157 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
158 	},
159 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
160 	  CONFIG_SYS_FSL_IFC_SIZE,
161 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
162 	},
163 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
164 	  CONFIG_SYS_FSL_DRAM_SIZE1,
165 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
166 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
167 #else	/* Start with nGnRnE and PXN and UXN to prevent speculative access */
168 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
169 #endif
170 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
171 	},
172 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
173 	  CONFIG_SYS_FSL_DRAM_SIZE2,
174 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
175 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
176 	},
177 #endif
178 	{},	/* list terminator */
179 };
180 
181 static struct mm_region final_map[] = {
182 #ifdef CONFIG_FSL_LSCH3
183 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
184 	  CONFIG_SYS_FSL_CCSR_SIZE,
185 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
186 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
187 	},
188 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
189 	  SYS_FSL_OCRAM_SPACE_SIZE,
190 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
191 	},
192 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
193 	  CONFIG_SYS_FSL_DRAM_SIZE1,
194 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
195 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
196 	},
197 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
198 	  CONFIG_SYS_FSL_QSPI_SIZE1,
199 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
200 	},
201 	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
202 	  CONFIG_SYS_FSL_QSPI_SIZE2,
203 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
204 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
205 	},
206 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
207 	  CONFIG_SYS_FSL_IFC_SIZE2,
208 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
209 	},
210 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
211 	  CONFIG_SYS_FSL_DCSR_SIZE,
212 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
213 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
214 	},
215 	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
216 	  CONFIG_SYS_FSL_MC_SIZE,
217 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
218 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
219 	},
220 	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
221 	  CONFIG_SYS_FSL_NI_SIZE,
222 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
223 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
224 	},
225 	/* For QBMAN portal, only the first 64MB is cache-enabled */
226 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
227 	  CONFIG_SYS_FSL_QBMAN_SIZE_1,
228 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
229 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
230 	},
231 	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
232 	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
233 	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
234 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
235 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
236 	},
237 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
238 	  CONFIG_SYS_PCIE1_PHYS_SIZE,
239 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
240 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
241 	},
242 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
243 	  CONFIG_SYS_PCIE2_PHYS_SIZE,
244 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
245 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
246 	},
247 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
248 	  CONFIG_SYS_PCIE3_PHYS_SIZE,
249 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
250 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
251 	},
252 #ifdef CONFIG_LS2080A
253 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
254 	  CONFIG_SYS_PCIE4_PHYS_SIZE,
255 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
256 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
257 	},
258 #endif
259 	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
260 	  CONFIG_SYS_FSL_WRIOP1_SIZE,
261 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
262 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
263 	},
264 	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
265 	  CONFIG_SYS_FSL_AIOP1_SIZE,
266 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
267 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
268 	},
269 	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
270 	  CONFIG_SYS_FSL_PEBUF_SIZE,
271 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
272 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
273 	},
274 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
275 	  CONFIG_SYS_FSL_DRAM_SIZE2,
276 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
277 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
278 	},
279 #elif defined(CONFIG_FSL_LSCH2)
280 	{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
281 	  CONFIG_SYS_FSL_BOOTROM_SIZE,
282 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
283 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
284 	},
285 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
286 	  CONFIG_SYS_FSL_CCSR_SIZE,
287 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
288 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
289 	},
290 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
291 	  SYS_FSL_OCRAM_SPACE_SIZE,
292 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
293 	},
294 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
295 	  CONFIG_SYS_FSL_DCSR_SIZE,
296 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
297 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
298 	},
299 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
300 	  CONFIG_SYS_FSL_QSPI_SIZE,
301 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
302 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
303 	},
304 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
305 	  CONFIG_SYS_FSL_IFC_SIZE,
306 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
307 	},
308 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
309 	  CONFIG_SYS_FSL_DRAM_SIZE1,
310 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
311 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
312 	},
313 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
314 	  CONFIG_SYS_FSL_QBMAN_SIZE,
315 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
316 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
317 	},
318 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
319 	  CONFIG_SYS_FSL_DRAM_SIZE2,
320 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
321 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
322 	},
323 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
324 	  CONFIG_SYS_PCIE1_PHYS_SIZE,
325 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
326 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
327 	},
328 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
329 	  CONFIG_SYS_PCIE2_PHYS_SIZE,
330 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
331 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
332 	},
333 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
334 	  CONFIG_SYS_PCIE3_PHYS_SIZE,
335 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
336 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
337 	},
338 	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
339 	  CONFIG_SYS_FSL_DRAM_SIZE3,
340 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
341 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
342 	},
343 #endif
344 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
345 	{},	/* space holder for secure mem */
346 #endif
347 	{},
348 };
349 #endif	/* !CONFIG_SYS_DCACHE_OFF */
350 
351 int fsl_qoriq_core_to_cluster(unsigned int core);
352 u32 cpu_mask(void);
353 #endif /* _FSL_LAYERSCAPE_CPU_H */
354