1 /* 2 * Copyright 2014-2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _FSL_LAYERSCAPE_CPU_H 8 #define _FSL_LAYERSCAPE_CPU_H 9 10 static struct cpu_type cpu_type_list[] = { 11 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), 12 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), 13 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), 14 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), 15 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), 16 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), 17 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), 18 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), 19 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), 20 }; 21 22 #ifndef CONFIG_SYS_DCACHE_OFF 23 24 #ifdef CONFIG_FSL_LSCH3 25 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 26 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 27 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 28 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 29 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 30 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 31 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 32 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 33 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 34 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 35 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 36 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 37 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 38 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 39 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 40 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 41 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000 42 #define CONFIG_SYS_FSL_NI_BASE 0x810000000 43 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000 44 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 45 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 46 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 47 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 48 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 49 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 50 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 51 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 52 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 53 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 54 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 55 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 56 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 57 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 58 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 59 #elif defined(CONFIG_FSL_LSCH2) 60 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 61 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 62 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 63 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 64 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 65 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 66 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 67 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 68 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 69 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 70 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 71 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 72 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 73 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 74 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 75 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ 76 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 77 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 78 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 79 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 80 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ 81 #endif 82 83 #define EARLY_PGTABLE_SIZE 0x5000 84 static struct mm_region early_map[] = { 85 #ifdef CONFIG_FSL_LSCH3 86 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 87 CONFIG_SYS_FSL_CCSR_SIZE, 88 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 89 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 90 }, 91 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 92 CONFIG_SYS_FSL_OCRAM_SIZE, 93 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 94 }, 95 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, 96 CONFIG_SYS_FSL_QSPI_SIZE1, 97 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, 98 /* For IFC Region #1, only the first 4MB is cache-enabled */ 99 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, 100 CONFIG_SYS_FSL_IFC_SIZE1_1, 101 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 102 }, 103 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 104 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 105 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, 106 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 107 }, 108 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, 109 CONFIG_SYS_FSL_IFC_SIZE1, 110 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 111 }, 112 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 113 CONFIG_SYS_FSL_DRAM_SIZE1, 114 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 115 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 116 }, 117 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ 118 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 119 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, 120 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 121 }, 122 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 123 CONFIG_SYS_FSL_DCSR_SIZE, 124 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 125 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 126 }, 127 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 128 CONFIG_SYS_FSL_DRAM_SIZE2, 129 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 130 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 131 }, 132 #elif defined(CONFIG_FSL_LSCH2) 133 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 134 CONFIG_SYS_FSL_CCSR_SIZE, 135 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 136 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 137 }, 138 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 139 CONFIG_SYS_FSL_OCRAM_SIZE, 140 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 141 }, 142 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 143 CONFIG_SYS_FSL_DCSR_SIZE, 144 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 145 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 146 }, 147 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 148 CONFIG_SYS_FSL_QSPI_SIZE, 149 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 150 }, 151 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 152 CONFIG_SYS_FSL_IFC_SIZE, 153 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 154 }, 155 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 156 CONFIG_SYS_FSL_DRAM_SIZE1, 157 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 158 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 159 }, 160 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 161 CONFIG_SYS_FSL_DRAM_SIZE2, 162 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 163 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 164 }, 165 #endif 166 {}, /* list terminator */ 167 }; 168 169 static struct mm_region final_map[] = { 170 #ifdef CONFIG_FSL_LSCH3 171 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 172 CONFIG_SYS_FSL_CCSR_SIZE, 173 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 174 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 175 }, 176 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 177 CONFIG_SYS_FSL_OCRAM_SIZE, 178 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 179 }, 180 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 181 CONFIG_SYS_FSL_DRAM_SIZE1, 182 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 183 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 184 }, 185 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, 186 CONFIG_SYS_FSL_QSPI_SIZE1, 187 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 188 }, 189 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, 190 CONFIG_SYS_FSL_QSPI_SIZE2, 191 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 192 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 193 }, 194 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 195 CONFIG_SYS_FSL_IFC_SIZE2, 196 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 197 }, 198 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 199 CONFIG_SYS_FSL_DCSR_SIZE, 200 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 201 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 202 }, 203 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, 204 CONFIG_SYS_FSL_MC_SIZE, 205 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 206 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 207 }, 208 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, 209 CONFIG_SYS_FSL_NI_SIZE, 210 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 211 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 212 }, 213 /* For QBMAN portal, only the first 64MB is cache-enabled */ 214 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 215 CONFIG_SYS_FSL_QBMAN_SIZE_1, 216 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 217 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS 218 }, 219 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 220 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 221 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, 222 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 223 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 224 }, 225 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 226 CONFIG_SYS_PCIE1_PHYS_SIZE, 227 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 228 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 229 }, 230 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 231 CONFIG_SYS_PCIE2_PHYS_SIZE, 232 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 233 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 234 }, 235 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 236 CONFIG_SYS_PCIE3_PHYS_SIZE, 237 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 238 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 239 }, 240 #ifdef CONFIG_LS2080A 241 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, 242 CONFIG_SYS_PCIE4_PHYS_SIZE, 243 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 244 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 245 }, 246 #endif 247 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, 248 CONFIG_SYS_FSL_WRIOP1_SIZE, 249 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 250 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 251 }, 252 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, 253 CONFIG_SYS_FSL_AIOP1_SIZE, 254 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 255 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 256 }, 257 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, 258 CONFIG_SYS_FSL_PEBUF_SIZE, 259 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 260 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 261 }, 262 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 263 CONFIG_SYS_FSL_DRAM_SIZE2, 264 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 265 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 266 }, 267 #elif defined(CONFIG_FSL_LSCH2) 268 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, 269 CONFIG_SYS_FSL_BOOTROM_SIZE, 270 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 271 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 272 }, 273 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 274 CONFIG_SYS_FSL_CCSR_SIZE, 275 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 276 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 277 }, 278 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 279 CONFIG_SYS_FSL_OCRAM_SIZE, 280 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 281 }, 282 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 283 CONFIG_SYS_FSL_DCSR_SIZE, 284 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 285 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 286 }, 287 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 288 CONFIG_SYS_FSL_QSPI_SIZE, 289 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 290 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 291 }, 292 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 293 CONFIG_SYS_FSL_IFC_SIZE, 294 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 295 }, 296 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 297 CONFIG_SYS_FSL_DRAM_SIZE1, 298 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 299 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 300 }, 301 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 302 CONFIG_SYS_FSL_QBMAN_SIZE, 303 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 304 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 305 }, 306 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 307 CONFIG_SYS_FSL_DRAM_SIZE2, 308 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 309 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 310 }, 311 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 312 CONFIG_SYS_PCIE1_PHYS_SIZE, 313 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 314 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 315 }, 316 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 317 CONFIG_SYS_PCIE2_PHYS_SIZE, 318 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 319 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 320 }, 321 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 322 CONFIG_SYS_PCIE3_PHYS_SIZE, 323 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 324 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 325 }, 326 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, 327 CONFIG_SYS_FSL_DRAM_SIZE3, 328 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 329 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 330 }, 331 #endif 332 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 333 {}, /* space holder for secure mem */ 334 #endif 335 {}, 336 }; 337 #endif /* !CONFIG_SYS_DCACHE_OFF */ 338 339 int fsl_qoriq_core_to_cluster(unsigned int core); 340 u32 cpu_mask(void); 341 #endif /* _FSL_LAYERSCAPE_CPU_H */ 342