1 /* 2 * Copyright 2014-2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _FSL_LAYERSCAPE_CPU_H 8 #define _FSL_LAYERSCAPE_CPU_H 9 10 static struct cpu_type cpu_type_list[] = { 11 CPU_TYPE_ENTRY(LS2080, LS2080, 8), 12 CPU_TYPE_ENTRY(LS2085, LS2085, 8), 13 CPU_TYPE_ENTRY(LS2045, LS2045, 4), 14 CPU_TYPE_ENTRY(LS1043, LS1043, 4), 15 }; 16 17 #ifndef CONFIG_SYS_DCACHE_OFF 18 19 #define SECTION_SHIFT_L0 39UL 20 #define SECTION_SHIFT_L1 30UL 21 #define SECTION_SHIFT_L2 21UL 22 #define BLOCK_SIZE_L0 0x8000000000 23 #define BLOCK_SIZE_L1 0x40000000 24 #define BLOCK_SIZE_L2 0x200000 25 #define NUM_OF_ENTRY 512 26 #define TCR_EL2_PS_40BIT (2 << 16) 27 28 #define LAYERSCAPE_VA_BITS (40) 29 #define LAYERSCAPE_TCR (TCR_TG0_4K | \ 30 TCR_EL2_PS_40BIT | \ 31 TCR_SHARED_NON | \ 32 TCR_ORGN_NC | \ 33 TCR_IRGN_NC | \ 34 TCR_T0SZ(LAYERSCAPE_VA_BITS)) 35 #define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \ 36 TCR_EL2_PS_40BIT | \ 37 TCR_SHARED_OUTER | \ 38 TCR_ORGN_WBWA | \ 39 TCR_IRGN_WBWA | \ 40 TCR_T0SZ(LAYERSCAPE_VA_BITS)) 41 42 #ifdef CONFIG_FSL_LSCH3 43 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 44 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 45 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 46 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 47 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 48 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 49 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 50 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 51 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 52 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 53 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 54 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 55 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 56 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 57 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 58 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 59 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000 60 #define CONFIG_SYS_FSL_NI_BASE 0x810000000 61 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000 62 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 63 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 64 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 65 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 66 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 67 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 68 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 69 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 70 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 71 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 72 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 73 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 74 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 75 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 76 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 77 #elif defined(CONFIG_FSL_LSCH2) 78 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 79 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 80 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 81 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 82 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 83 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 84 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 85 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 86 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 87 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 88 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 89 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 90 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 91 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 92 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 93 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ 94 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 95 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 96 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 97 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 98 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ 99 #endif 100 101 struct sys_mmu_table { 102 u64 virt_addr; 103 u64 phys_addr; 104 u64 size; 105 u64 memory_type; 106 u64 attribute; 107 }; 108 109 struct table_info { 110 u64 *ptr; 111 u64 table_base; 112 u64 entry_size; 113 }; 114 115 static const struct sys_mmu_table early_mmu_table[] = { 116 #ifdef CONFIG_FSL_LSCH3 117 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 118 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 119 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 120 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 121 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, 122 /* For IFC Region #1, only the first 4MB is cache-enabled */ 123 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, 124 CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, 125 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 126 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 127 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, 128 MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, 129 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, 130 CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, 131 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 132 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, 133 PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, 134 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ 135 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 136 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, 137 MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, 138 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 139 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 140 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 141 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 142 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, 143 PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, 144 #elif defined(CONFIG_FSL_LSCH2) 145 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 146 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 147 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 148 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 149 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, 150 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 151 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 152 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 153 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 154 CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, 155 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 156 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, 157 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 158 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, 159 #endif 160 }; 161 162 static const struct sys_mmu_table final_mmu_table[] = { 163 #ifdef CONFIG_FSL_LSCH3 164 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 165 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 166 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 167 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 168 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, 169 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 170 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, 171 PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, 172 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, 173 CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, 174 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 175 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 176 CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, 177 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 178 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 179 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 180 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, 181 CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, 182 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 183 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, 184 CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, 185 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 186 /* For QBMAN portal, only the first 64MB is cache-enabled */ 187 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 188 CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, 189 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN | PMD_SECT_NS }, 190 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 191 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 192 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, 193 MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 194 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 195 CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, 196 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 197 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 198 CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, 199 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 200 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 201 CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, 202 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 203 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 204 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, 205 CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, 206 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 207 #endif 208 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, 209 CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, 210 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 211 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, 212 CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, 213 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 214 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, 215 CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, 216 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 217 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 218 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, 219 PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, 220 #elif defined(CONFIG_FSL_LSCH2) 221 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, 222 CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, 223 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 224 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 225 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 226 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 227 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 228 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, 229 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 230 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 231 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 232 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 233 CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, 234 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 235 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 236 CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, 237 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 238 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, 239 PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, 240 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 241 CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, 242 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 243 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 244 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, 245 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 246 CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, 247 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 248 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 249 CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, 250 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 251 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 252 CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, 253 PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, 254 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, 255 CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, 256 #endif 257 }; 258 #endif 259 260 int fsl_qoriq_core_to_cluster(unsigned int core); 261 u32 cpu_mask(void); 262 #endif /* _FSL_LAYERSCAPE_CPU_H */ 263