1 /* 2 * Copyright 2017 NXP 3 * Copyright 2014-2015, Freescale Semiconductor 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _FSL_LAYERSCAPE_CPU_H 9 #define _FSL_LAYERSCAPE_CPU_H 10 11 static struct cpu_type cpu_type_list[] = { 12 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), 13 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), 14 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), 15 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8), 16 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8), 17 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4), 18 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4), 19 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8), 20 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4), 21 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), 22 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), 23 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), 24 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), 25 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), 26 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), 27 }; 28 29 #ifndef CONFIG_SYS_DCACHE_OFF 30 31 #ifdef CONFIG_FSL_LSCH3 32 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 33 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 34 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 35 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 36 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 37 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 38 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 39 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 40 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 41 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 42 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 43 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 44 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 45 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 46 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 47 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 48 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000 49 #define CONFIG_SYS_FSL_NI_BASE 0x810000000 50 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000 51 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 52 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 53 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 54 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 55 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 56 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 57 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 58 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 59 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 60 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 61 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 62 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 63 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 64 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 65 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 66 #elif defined(CONFIG_FSL_LSCH2) 67 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 68 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 69 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 70 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 71 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 72 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 73 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 74 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 75 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 76 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 77 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 78 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 79 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 80 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 81 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 82 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ 83 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 84 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 85 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 86 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 87 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ 88 #endif 89 90 #define EARLY_PGTABLE_SIZE 0x5000 91 static struct mm_region early_map[] = { 92 #ifdef CONFIG_FSL_LSCH3 93 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 94 CONFIG_SYS_FSL_CCSR_SIZE, 95 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 96 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 97 }, 98 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 99 SYS_FSL_OCRAM_SPACE_SIZE, 100 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 101 }, 102 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, 103 CONFIG_SYS_FSL_QSPI_SIZE1, 104 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, 105 /* For IFC Region #1, only the first 4MB is cache-enabled */ 106 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, 107 CONFIG_SYS_FSL_IFC_SIZE1_1, 108 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 109 }, 110 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 111 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 112 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, 113 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 114 }, 115 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, 116 CONFIG_SYS_FSL_IFC_SIZE1, 117 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 118 }, 119 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 120 CONFIG_SYS_FSL_DRAM_SIZE1, 121 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 122 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 123 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ 124 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | 125 #endif 126 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 127 }, 128 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ 129 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 130 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, 131 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 132 }, 133 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 134 CONFIG_SYS_FSL_DCSR_SIZE, 135 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 136 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 137 }, 138 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 139 CONFIG_SYS_FSL_DRAM_SIZE2, 140 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | 141 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 142 }, 143 #elif defined(CONFIG_FSL_LSCH2) 144 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 145 CONFIG_SYS_FSL_CCSR_SIZE, 146 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 147 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 148 }, 149 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 150 SYS_FSL_OCRAM_SPACE_SIZE, 151 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 152 }, 153 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 154 CONFIG_SYS_FSL_DCSR_SIZE, 155 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 156 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 157 }, 158 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 159 CONFIG_SYS_FSL_QSPI_SIZE, 160 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 161 }, 162 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 163 CONFIG_SYS_FSL_IFC_SIZE, 164 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 165 }, 166 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 167 CONFIG_SYS_FSL_DRAM_SIZE1, 168 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 169 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 170 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ 171 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | 172 #endif 173 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 174 }, 175 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 176 CONFIG_SYS_FSL_DRAM_SIZE2, 177 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | 178 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 179 }, 180 #endif 181 {}, /* list terminator */ 182 }; 183 184 static struct mm_region final_map[] = { 185 #ifdef CONFIG_FSL_LSCH3 186 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 187 CONFIG_SYS_FSL_CCSR_SIZE, 188 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 189 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 190 }, 191 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 192 SYS_FSL_OCRAM_SPACE_SIZE, 193 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 194 }, 195 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 196 CONFIG_SYS_FSL_DRAM_SIZE1, 197 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 198 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 199 }, 200 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, 201 CONFIG_SYS_FSL_QSPI_SIZE1, 202 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 203 }, 204 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, 205 CONFIG_SYS_FSL_QSPI_SIZE2, 206 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 207 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 208 }, 209 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 210 CONFIG_SYS_FSL_IFC_SIZE2, 211 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 212 }, 213 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 214 CONFIG_SYS_FSL_DCSR_SIZE, 215 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 216 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 217 }, 218 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, 219 CONFIG_SYS_FSL_MC_SIZE, 220 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 221 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 222 }, 223 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, 224 CONFIG_SYS_FSL_NI_SIZE, 225 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 226 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 227 }, 228 /* For QBMAN portal, only the first 64MB is cache-enabled */ 229 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 230 CONFIG_SYS_FSL_QBMAN_SIZE_1, 231 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 232 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS 233 }, 234 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 235 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 236 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, 237 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 238 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 239 }, 240 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 241 CONFIG_SYS_PCIE1_PHYS_SIZE, 242 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 243 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 244 }, 245 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 246 CONFIG_SYS_PCIE2_PHYS_SIZE, 247 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 248 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 249 }, 250 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 251 CONFIG_SYS_PCIE3_PHYS_SIZE, 252 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 253 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 254 }, 255 #ifdef CONFIG_ARCH_LS2080A 256 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, 257 CONFIG_SYS_PCIE4_PHYS_SIZE, 258 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 259 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 260 }, 261 #endif 262 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, 263 CONFIG_SYS_FSL_WRIOP1_SIZE, 264 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 265 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 266 }, 267 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, 268 CONFIG_SYS_FSL_AIOP1_SIZE, 269 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 270 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 271 }, 272 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, 273 CONFIG_SYS_FSL_PEBUF_SIZE, 274 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 275 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 276 }, 277 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 278 CONFIG_SYS_FSL_DRAM_SIZE2, 279 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 280 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 281 }, 282 #elif defined(CONFIG_FSL_LSCH2) 283 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, 284 CONFIG_SYS_FSL_BOOTROM_SIZE, 285 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 286 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 287 }, 288 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 289 CONFIG_SYS_FSL_CCSR_SIZE, 290 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 291 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 292 }, 293 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 294 SYS_FSL_OCRAM_SPACE_SIZE, 295 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 296 }, 297 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 298 CONFIG_SYS_FSL_DCSR_SIZE, 299 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 300 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 301 }, 302 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 303 CONFIG_SYS_FSL_QSPI_SIZE, 304 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 305 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 306 }, 307 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 308 CONFIG_SYS_FSL_IFC_SIZE, 309 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 310 }, 311 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 312 CONFIG_SYS_FSL_DRAM_SIZE1, 313 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 314 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 315 }, 316 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 317 CONFIG_SYS_FSL_QBMAN_SIZE, 318 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 319 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 320 }, 321 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 322 CONFIG_SYS_FSL_DRAM_SIZE2, 323 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 324 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 325 }, 326 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 327 CONFIG_SYS_PCIE1_PHYS_SIZE, 328 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 329 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 330 }, 331 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 332 CONFIG_SYS_PCIE2_PHYS_SIZE, 333 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 334 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 335 }, 336 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 337 CONFIG_SYS_PCIE3_PHYS_SIZE, 338 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 339 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 340 }, 341 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, 342 CONFIG_SYS_FSL_DRAM_SIZE3, 343 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 344 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 345 }, 346 #endif 347 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 348 {}, /* space holder for secure mem */ 349 #endif 350 {}, 351 }; 352 #endif /* !CONFIG_SYS_DCACHE_OFF */ 353 354 int fsl_qoriq_core_to_cluster(unsigned int core); 355 u32 cpu_mask(void); 356 357 #endif /* _FSL_LAYERSCAPE_CPU_H */ 358