1 /*
2  * Copyright 2014-2015, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
9 
10 static struct cpu_type cpu_type_list[] = {
11 	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
12 	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
13 	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
14 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
15 	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
16 	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
17 	CPU_TYPE_ENTRY(LS1012, LS1012, 1),
18 };
19 
20 #ifndef CONFIG_SYS_DCACHE_OFF
21 
22 #define SECTION_SHIFT_L0		39UL
23 #define SECTION_SHIFT_L1		30UL
24 #define SECTION_SHIFT_L2		21UL
25 #define BLOCK_SIZE_L0			0x8000000000
26 #define BLOCK_SIZE_L1			0x40000000
27 #define BLOCK_SIZE_L2			0x200000
28 #define NUM_OF_ENTRY			512
29 #define TCR_EL2_PS_40BIT		(2 << 16)
30 
31 #define LAYERSCAPE_VA_BITS		(40)
32 #define LAYERSCAPE_TCR		(TCR_TG0_4K		| \
33 				TCR_EL2_PS_40BIT	| \
34 				TCR_SHARED_NON		| \
35 				TCR_ORGN_NC		| \
36 				TCR_IRGN_NC		| \
37 				TCR_T0SZ(LAYERSCAPE_VA_BITS))
38 #define LAYERSCAPE_TCR_FINAL	(TCR_TG0_4K		| \
39 				TCR_EL2_PS_40BIT	| \
40 				TCR_SHARED_OUTER	| \
41 				TCR_ORGN_WBWA		| \
42 				TCR_IRGN_WBWA		| \
43 				TCR_T0SZ(LAYERSCAPE_VA_BITS))
44 
45 #ifdef CONFIG_FSL_LSCH3
46 #define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
47 #define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
48 #define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
49 #define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
50 #define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
51 #define CONFIG_SYS_FSL_IFC_SIZE1	0x10000000
52 #define CONFIG_SYS_FSL_IFC_SIZE1_1	0x400000
53 #define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
54 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
55 #define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
56 #define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
57 #define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
58 #define CONFIG_SYS_FSL_IFC_SIZE2	0x100000000
59 #define CONFIG_SYS_FSL_DCSR_BASE	0x700000000
60 #define CONFIG_SYS_FSL_DCSR_SIZE	0x40000000
61 #define CONFIG_SYS_FSL_MC_BASE		0x80c000000
62 #define CONFIG_SYS_FSL_MC_SIZE		0x4000000
63 #define CONFIG_SYS_FSL_NI_BASE		0x810000000
64 #define CONFIG_SYS_FSL_NI_SIZE		0x8000000
65 #define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
66 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
67 #define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
68 #define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
69 #define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
70 #define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
71 #define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
72 #define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
73 #define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
74 #define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
75 #define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
76 #define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
77 #define CONFIG_SYS_FSL_PEBUF_SIZE	0x400000000
78 #define CONFIG_SYS_FSL_DRAM_BASE2	0x8080000000
79 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x7F80000000
80 #elif defined(CONFIG_FSL_LSCH2)
81 #define CONFIG_SYS_FSL_BOOTROM_BASE	0x0
82 #define CONFIG_SYS_FSL_BOOTROM_SIZE	0x1000000
83 #define CONFIG_SYS_FSL_CCSR_BASE	0x1000000
84 #define CONFIG_SYS_FSL_CCSR_SIZE	0xf000000
85 #define CONFIG_SYS_FSL_DCSR_BASE	0x20000000
86 #define CONFIG_SYS_FSL_DCSR_SIZE	0x4000000
87 #define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
88 #define CONFIG_SYS_FSL_QSPI_SIZE	0x20000000
89 #define CONFIG_SYS_FSL_IFC_BASE		0x60000000
90 #define CONFIG_SYS_FSL_IFC_SIZE		0x20000000
91 #define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
92 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
93 #define CONFIG_SYS_FSL_QBMAN_BASE	0x500000000
94 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
95 #define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
96 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
97 #define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
98 #define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
99 #define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
100 #define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
101 #define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
102 #endif
103 
104 struct sys_mmu_table {
105 	u64 virt_addr;
106 	u64 phys_addr;
107 	u64 size;
108 	u64 memory_type;
109 	u64 attribute;
110 };
111 
112 struct table_info {
113 	u64 *ptr;
114 	u64 table_base;
115 	u64 entry_size;
116 };
117 
118 static const struct sys_mmu_table early_mmu_table[] = {
119 #ifdef CONFIG_FSL_LSCH3
120 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
121 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
122 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
123 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
124 	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
125 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
126 	  CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
127 	/* For IFC Region #1, only the first 4MB is cache-enabled */
128 	{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
129 	  CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
130 	{ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
131 	  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
132 	  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
133 	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
134 	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
135 	  CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
136 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
137 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
138 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
139 	/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
140 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
141 	  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
142 	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
143 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
144 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
145 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
146 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
147 	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
148 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
149 #elif defined(CONFIG_FSL_LSCH2)
150 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
151 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
152 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
153 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
154 	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
155 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
156 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
157 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
158 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
159 	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
160 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
161 	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
162 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
163 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
164 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
165 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
166 	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
167 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
168 #endif
169 };
170 
171 static const struct sys_mmu_table final_mmu_table[] = {
172 #ifdef CONFIG_FSL_LSCH3
173 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
174 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
175 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
176 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
177 	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
178 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
179 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
180 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
181 	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
182 	  CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
183 	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
184 	  CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
185 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
186 	{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
187 	  CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
188 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
189 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
190 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
191 	{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
192 	  CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
193 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
194 	{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
195 	  CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
196 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
197 	/* For QBMAN portal, only the first 64MB is cache-enabled */
198 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
199 	  CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
200 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS },
201 	{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
202 	  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
203 	  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
204 	  MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
205 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
206 	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
207 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
208 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
209 	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
210 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
211 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
212 	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
213 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
214 #ifdef CONFIG_LS2080A
215 	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
216 	  CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
217 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
218 #endif
219 	{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
220 	  CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
221 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
222 	{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
223 	  CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
224 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
225 	{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
226 	  CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
227 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
228 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
229 	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
230 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
231 #elif defined(CONFIG_FSL_LSCH2)
232 	{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
233 	  CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
234 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
235 	{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
236 	  CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
237 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
238 	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
239 	  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
240 	{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
241 	  CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
242 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
243 	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
244 	  CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
245 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
246 	{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
247 	  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
248 	{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
249 	  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
250 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
251 	{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
252 	  CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
253 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
254 	{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
255 	  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
256 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
257 	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
258 	  CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
259 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
260 	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
261 	  CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
262 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
263 	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
264 	  CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
265 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
266 	{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
267 	  CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
268 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
269 #endif
270 };
271 #endif
272 
273 int fsl_qoriq_core_to_cluster(unsigned int core);
274 u32 cpu_mask(void);
275 #endif /* _FSL_LAYERSCAPE_CPU_H */
276