1 /* 2 * Copyright 2014-2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _FSL_LAYERSCAPE_CPU_H 8 #define _FSL_LAYERSCAPE_CPU_H 9 10 static struct cpu_type cpu_type_list[] = { 11 CPU_TYPE_ENTRY(LS2080, LS2080, 8), 12 CPU_TYPE_ENTRY(LS2085, LS2085, 8), 13 CPU_TYPE_ENTRY(LS2045, LS2045, 4), 14 CPU_TYPE_ENTRY(LS1043, LS1043, 4), 15 CPU_TYPE_ENTRY(LS1023, LS1023, 2), 16 CPU_TYPE_ENTRY(LS2040, LS2040, 4), 17 }; 18 19 #ifndef CONFIG_SYS_DCACHE_OFF 20 21 #define SECTION_SHIFT_L0 39UL 22 #define SECTION_SHIFT_L1 30UL 23 #define SECTION_SHIFT_L2 21UL 24 #define BLOCK_SIZE_L0 0x8000000000 25 #define BLOCK_SIZE_L1 0x40000000 26 #define BLOCK_SIZE_L2 0x200000 27 #define NUM_OF_ENTRY 512 28 #define TCR_EL2_PS_40BIT (2 << 16) 29 30 #define LAYERSCAPE_VA_BITS (40) 31 #define LAYERSCAPE_TCR (TCR_TG0_4K | \ 32 TCR_EL2_PS_40BIT | \ 33 TCR_SHARED_NON | \ 34 TCR_ORGN_NC | \ 35 TCR_IRGN_NC | \ 36 TCR_T0SZ(LAYERSCAPE_VA_BITS)) 37 #define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \ 38 TCR_EL2_PS_40BIT | \ 39 TCR_SHARED_OUTER | \ 40 TCR_ORGN_WBWA | \ 41 TCR_IRGN_WBWA | \ 42 TCR_T0SZ(LAYERSCAPE_VA_BITS)) 43 44 #ifdef CONFIG_FSL_LSCH3 45 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 46 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 47 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 48 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 49 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 50 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 51 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 52 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 53 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 54 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 55 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 56 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 57 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 58 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 59 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 60 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 61 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000 62 #define CONFIG_SYS_FSL_NI_BASE 0x810000000 63 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000 64 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 65 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 66 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 67 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 68 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 69 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 70 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 71 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 72 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 73 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 74 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 75 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 76 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 77 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 78 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 79 #elif defined(CONFIG_FSL_LSCH2) 80 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 81 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 82 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 83 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 84 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 85 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 86 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 87 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 88 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 89 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 90 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 91 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 92 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 93 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 94 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 95 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ 96 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 97 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 98 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 99 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 100 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ 101 #endif 102 103 struct sys_mmu_table { 104 u64 virt_addr; 105 u64 phys_addr; 106 u64 size; 107 u64 memory_type; 108 u64 attribute; 109 }; 110 111 struct table_info { 112 u64 *ptr; 113 u64 table_base; 114 u64 entry_size; 115 }; 116 117 static const struct sys_mmu_table early_mmu_table[] = { 118 #ifdef CONFIG_FSL_LSCH3 119 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 120 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 121 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 122 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 123 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, 124 /* For IFC Region #1, only the first 4MB is cache-enabled */ 125 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, 126 CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE }, 127 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 128 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 129 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, 130 MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, 131 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, 132 CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, 133 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 134 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, 135 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, 136 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ 137 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 138 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, 139 MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, 140 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 141 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 142 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 143 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 144 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, 145 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, 146 #elif defined(CONFIG_FSL_LSCH2) 147 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 148 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 149 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 150 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 151 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, 152 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 153 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 154 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 155 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 156 CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, 157 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 158 CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, 159 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 160 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, 161 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 162 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, 163 #endif 164 }; 165 166 static const struct sys_mmu_table final_mmu_table[] = { 167 #ifdef CONFIG_FSL_LSCH3 168 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 169 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 170 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 171 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 172 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, 173 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 174 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, 175 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, 176 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, 177 CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, 178 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 179 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 180 CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, 181 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 182 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 183 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 184 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, 185 CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, 186 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 187 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, 188 CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, 189 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 190 /* For QBMAN portal, only the first 64MB is cache-enabled */ 191 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 192 CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, 193 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS }, 194 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 195 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 196 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, 197 MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 198 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 199 CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, 200 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 201 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 202 CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, 203 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 204 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 205 CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, 206 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 207 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 208 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, 209 CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, 210 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 211 #endif 212 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, 213 CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, 214 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 215 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, 216 CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, 217 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 218 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, 219 CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, 220 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 221 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 222 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, 223 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, 224 #elif defined(CONFIG_FSL_LSCH2) 225 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, 226 CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, 227 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 228 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 229 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, 230 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 231 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 232 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, 233 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 234 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, 235 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 236 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 237 CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, 238 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 239 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 240 CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, 241 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 242 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, 243 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, 244 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 245 CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, 246 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 247 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 248 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, 249 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 250 CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, 251 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 252 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 253 CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, 254 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 255 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 256 CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, 257 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, 258 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, 259 CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, 260 #endif 261 }; 262 #endif 263 264 int fsl_qoriq_core_to_cluster(unsigned int core); 265 u32 cpu_mask(void); 266 #endif /* _FSL_LAYERSCAPE_CPU_H */ 267