1 /* 2 * Copyright 2014-2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _FSL_LAYERSCAPE_CPU_H 8 #define _FSL_LAYERSCAPE_CPU_H 9 10 static struct cpu_type cpu_type_list[] = { 11 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), 12 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), 13 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), 14 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), 15 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), 16 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), 17 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), 18 }; 19 20 #ifndef CONFIG_SYS_DCACHE_OFF 21 22 #ifdef CONFIG_FSL_LSCH3 23 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 24 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 25 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 26 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 27 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 28 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 29 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 30 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 31 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 32 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 33 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 34 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 35 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 36 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 37 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 38 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 39 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000 40 #define CONFIG_SYS_FSL_NI_BASE 0x810000000 41 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000 42 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 43 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 44 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 45 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 46 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 47 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 49 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 50 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 51 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 52 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 53 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 54 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 55 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 56 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 57 #elif defined(CONFIG_FSL_LSCH2) 58 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 59 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 60 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 61 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 62 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 63 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 64 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 65 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 66 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 67 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 68 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 69 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 70 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 71 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 72 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 73 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ 74 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 75 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 76 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 77 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 78 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ 79 #endif 80 81 #define EARLY_PGTABLE_SIZE 0x5000 82 static struct mm_region early_map[] = { 83 #ifdef CONFIG_FSL_LSCH3 84 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 85 CONFIG_SYS_FSL_CCSR_SIZE, 86 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 87 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 88 }, 89 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 90 CONFIG_SYS_FSL_OCRAM_SIZE, 91 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 92 }, 93 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, 94 CONFIG_SYS_FSL_QSPI_SIZE1, 95 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, 96 /* For IFC Region #1, only the first 4MB is cache-enabled */ 97 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, 98 CONFIG_SYS_FSL_IFC_SIZE1_1, 99 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 100 }, 101 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 102 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, 103 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, 104 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 105 }, 106 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, 107 CONFIG_SYS_FSL_IFC_SIZE1, 108 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 109 }, 110 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 111 CONFIG_SYS_FSL_DRAM_SIZE1, 112 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 113 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 114 }, 115 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ 116 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 117 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, 118 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 119 }, 120 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 121 CONFIG_SYS_FSL_DCSR_SIZE, 122 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 123 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 124 }, 125 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 126 CONFIG_SYS_FSL_DRAM_SIZE2, 127 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 128 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 129 }, 130 #elif defined(CONFIG_FSL_LSCH2) 131 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 132 CONFIG_SYS_FSL_CCSR_SIZE, 133 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 134 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 135 }, 136 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 137 CONFIG_SYS_FSL_OCRAM_SIZE, 138 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 139 }, 140 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 141 CONFIG_SYS_FSL_DCSR_SIZE, 142 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 143 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 144 }, 145 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 146 CONFIG_SYS_FSL_QSPI_SIZE, 147 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 148 }, 149 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 150 CONFIG_SYS_FSL_IFC_SIZE, 151 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 152 }, 153 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 154 CONFIG_SYS_FSL_DRAM_SIZE1, 155 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 156 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 157 }, 158 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 159 CONFIG_SYS_FSL_DRAM_SIZE2, 160 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 161 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 162 }, 163 #endif 164 {}, /* list terminator */ 165 }; 166 167 static struct mm_region final_map[] = { 168 #ifdef CONFIG_FSL_LSCH3 169 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 170 CONFIG_SYS_FSL_CCSR_SIZE, 171 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 172 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 173 }, 174 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 175 CONFIG_SYS_FSL_OCRAM_SIZE, 176 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 177 }, 178 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 179 CONFIG_SYS_FSL_DRAM_SIZE1, 180 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 181 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 182 }, 183 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, 184 CONFIG_SYS_FSL_QSPI_SIZE1, 185 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 186 }, 187 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, 188 CONFIG_SYS_FSL_QSPI_SIZE2, 189 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 190 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 191 }, 192 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, 193 CONFIG_SYS_FSL_IFC_SIZE2, 194 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 195 }, 196 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 197 CONFIG_SYS_FSL_DCSR_SIZE, 198 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 199 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 200 }, 201 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, 202 CONFIG_SYS_FSL_MC_SIZE, 203 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 204 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 205 }, 206 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, 207 CONFIG_SYS_FSL_NI_SIZE, 208 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 209 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 210 }, 211 /* For QBMAN portal, only the first 64MB is cache-enabled */ 212 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 213 CONFIG_SYS_FSL_QBMAN_SIZE_1, 214 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 215 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS 216 }, 217 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 218 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, 219 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, 220 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 221 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 222 }, 223 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 224 CONFIG_SYS_PCIE1_PHYS_SIZE, 225 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 226 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 227 }, 228 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 229 CONFIG_SYS_PCIE2_PHYS_SIZE, 230 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 231 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 232 }, 233 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 234 CONFIG_SYS_PCIE3_PHYS_SIZE, 235 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 236 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 237 }, 238 #ifdef CONFIG_LS2080A 239 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, 240 CONFIG_SYS_PCIE4_PHYS_SIZE, 241 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 242 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 243 }, 244 #endif 245 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, 246 CONFIG_SYS_FSL_WRIOP1_SIZE, 247 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 248 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 249 }, 250 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, 251 CONFIG_SYS_FSL_AIOP1_SIZE, 252 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 253 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 254 }, 255 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, 256 CONFIG_SYS_FSL_PEBUF_SIZE, 257 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 258 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 259 }, 260 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 261 CONFIG_SYS_FSL_DRAM_SIZE2, 262 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 263 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 264 }, 265 #elif defined(CONFIG_FSL_LSCH2) 266 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, 267 CONFIG_SYS_FSL_BOOTROM_SIZE, 268 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 269 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 270 }, 271 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, 272 CONFIG_SYS_FSL_CCSR_SIZE, 273 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 274 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 275 }, 276 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, 277 CONFIG_SYS_FSL_OCRAM_SIZE, 278 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE 279 }, 280 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, 281 CONFIG_SYS_FSL_DCSR_SIZE, 282 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 283 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 284 }, 285 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, 286 CONFIG_SYS_FSL_QSPI_SIZE, 287 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 288 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 289 }, 290 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, 291 CONFIG_SYS_FSL_IFC_SIZE, 292 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE 293 }, 294 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, 295 CONFIG_SYS_FSL_DRAM_SIZE1, 296 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 297 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 298 }, 299 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, 300 CONFIG_SYS_FSL_QBMAN_SIZE, 301 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 302 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 303 }, 304 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, 305 CONFIG_SYS_FSL_DRAM_SIZE2, 306 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 307 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 308 }, 309 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, 310 CONFIG_SYS_PCIE1_PHYS_SIZE, 311 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 312 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 313 }, 314 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, 315 CONFIG_SYS_PCIE2_PHYS_SIZE, 316 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 317 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 318 }, 319 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, 320 CONFIG_SYS_PCIE3_PHYS_SIZE, 321 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 322 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN 323 }, 324 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, 325 CONFIG_SYS_FSL_DRAM_SIZE3, 326 PTE_BLOCK_MEMTYPE(MT_NORMAL) | 327 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS 328 }, 329 #endif 330 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 331 {}, /* space holder for secure mem */ 332 #endif 333 {}, 334 }; 335 #endif /* !CONFIG_SYS_DCACHE_OFF */ 336 337 int fsl_qoriq_core_to_cluster(unsigned int core); 338 u32 cpu_mask(void); 339 #endif /* _FSL_LAYERSCAPE_CPU_H */ 340