1 /*
2  * Copyright 2015, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
9 
10 #include <fsl_ddrc_version.h>
11 
12 #ifdef CONFIG_SYS_FSL_DDR4
13 #define CONFIG_SYS_FSL_DDRC_GEN4
14 #else
15 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
16 #endif
17 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
18 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
19 
20 /*
21  * Reserve secure memory
22  * To be aligned with MMU block size
23  */
24 #define CONFIG_SYS_MEM_RESERVE_SECURE	(2048 * 1024)	/* 2MB */
25 
26 #ifdef CONFIG_LS2080A
27 #define CONFIG_MAX_CPUS				16
28 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
29 #define CONFIG_NUM_DDR_CONTROLLERS		3
30 #define CONFIG_SYS_FSL_HAS_DP_DDR		/* Runtime check to confirm */
31 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
32 #define	SRDS_MAX_LANES	8
33 #define CONFIG_SYS_FSL_SRDS_1
34 #define CONFIG_SYS_FSL_SRDS_2
35 #define CONFIG_SYS_PAGE_SIZE		0x10000
36 #define CONFIG_SYS_CACHELINE_SIZE	64
37 #ifndef L1_CACHE_BYTES
38 #define L1_CACHE_SHIFT		6
39 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
40 #endif
41 
42 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
43 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
44 
45 /* DDR */
46 #define CONFIG_SYS_FSL_DDR_LE
47 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
48 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
49 
50 #define CONFIG_SYS_FSL_CCSR_GUR_LE
51 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
52 #define CONFIG_SYS_FSL_ESDHC_LE
53 #define CONFIG_SYS_FSL_IFC_LE
54 #define CONFIG_SYS_FSL_PEX_LUT_LE
55 
56 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
57 
58 /* Generic Interrupt Controller Definitions */
59 #define GICD_BASE			0x06000000
60 #define GICR_BASE			0x06100000
61 
62 /* SMMU Defintions */
63 #define SMMU_BASE			0x05000000 /* GR0 Base */
64 
65 /* SFP */
66 #define CONFIG_SYS_FSL_SFP_VER_3_4
67 #define CONFIG_SYS_FSL_SFP_LE
68 #define CONFIG_SYS_FSL_SRK_LE
69 
70 /* SEC */
71 #define CONFIG_SYS_FSL_SEC_LE
72 #define CONFIG_SYS_FSL_SEC_COMPAT	5
73 
74 /* Security Monitor */
75 #define CONFIG_SYS_FSL_SEC_MON_LE
76 
77 /* Secure Boot */
78 #define CONFIG_ESBC_HDR_LS
79 
80 /* DCFG - GUR */
81 #define CONFIG_SYS_FSL_CCSR_GUR_LE
82 
83 /* Cache Coherent Interconnect */
84 #define CCI_MN_BASE			0x04000000
85 #define CCI_MN_RNF_NODEID_LIST		0x180
86 #define CCI_MN_DVM_DOMAIN_CTL		0x200
87 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
88 
89 #define CCI_HN_F_0_BASE			(CCI_MN_BASE + 0x200000)
90 #define CCI_HN_F_1_BASE			(CCI_MN_BASE + 0x210000)
91 #define CCN_HN_F_SAM_CTL		0x8	/* offset on base HN_F base */
92 #define CCN_HN_F_SAM_NODEID_MASK	0x7f
93 #define CCN_HN_F_SAM_NODEID_DDR0	0x4
94 #define CCN_HN_F_SAM_NODEID_DDR1	0xe
95 
96 #define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
97 #define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
98 #define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
99 #define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
100 #define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
101 #define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
102 
103 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
104 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
105 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
106 
107 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
108 
109 /* TZ Protection Controller Definitions */
110 #define TZPC_BASE				0x02200000
111 #define TZPCR0SIZE_BASE				(TZPC_BASE)
112 #define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
113 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
114 #define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
115 #define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
116 #define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
117 #define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
118 #define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
119 #define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
120 #define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
121 
122 #define DCSR_CGACRE5		0x700070914ULL
123 #define EPU_EPCMPR5		0x700060914ULL
124 #define EPU_EPCCR5		0x700060814ULL
125 #define EPU_EPSMCR5		0x700060228ULL
126 #define EPU_EPECR5		0x700060314ULL
127 #define EPU_EPCTR5		0x700060a14ULL
128 #define EPU_EPGCR		0x700060000ULL
129 
130 #define CONFIG_SYS_FSL_ERRATUM_A008336
131 #define CONFIG_SYS_FSL_ERRATUM_A008511
132 #define CONFIG_SYS_FSL_ERRATUM_A008514
133 #define CONFIG_SYS_FSL_ERRATUM_A008585
134 #define CONFIG_SYS_FSL_ERRATUM_A008751
135 #define CONFIG_SYS_FSL_ERRATUM_A009635
136 #define CONFIG_SYS_FSL_ERRATUM_A009663
137 #define CONFIG_SYS_FSL_ERRATUM_A009801
138 #define CONFIG_SYS_FSL_ERRATUM_A009803
139 #define CONFIG_SYS_FSL_ERRATUM_A009942
140 #define CONFIG_SYS_FSL_ERRATUM_A010165
141 
142 /* ARM A57 CORE ERRATA */
143 #define CONFIG_ARM_ERRATA_826974
144 #define CONFIG_ARM_ERRATA_828024
145 #define CONFIG_ARM_ERRATA_829520
146 #define CONFIG_ARM_ERRATA_833471
147 
148 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
149 #elif defined(CONFIG_LS1043A)
150 #define CONFIG_MAX_CPUS				4
151 #define CONFIG_SYS_CACHELINE_SIZE		64
152 #define CONFIG_SYS_FMAN_V3
153 #define CONFIG_SYS_NUM_FMAN			1
154 #define CONFIG_SYS_NUM_FM1_DTSEC		7
155 #define CONFIG_SYS_NUM_FM1_10GEC		1
156 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
157 #define CONFIG_NUM_DDR_CONTROLLERS		1
158 #define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
159 #define CONFIG_SYS_FSL_SEC_COMPAT		5
160 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
161 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
162 #define CONFIG_SYS_FSL_DDR_BE
163 #define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
164 #define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
165 
166 #define CONFIG_SYS_FSL_CCSR_GUR_BE
167 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
168 #define CONFIG_SYS_FSL_IFC_BE
169 #define CONFIG_SYS_FSL_ESDHC_BE
170 #define CONFIG_SYS_FSL_WDOG_BE
171 #define CONFIG_SYS_FSL_DSPI_BE
172 #define CONFIG_SYS_FSL_QSPI_BE
173 #define CONFIG_SYS_FSL_PEX_LUT_BE
174 
175 #define QE_MURAM_SIZE		0x6000UL
176 #define MAX_QE_RISC		1
177 #define QE_NUM_OF_SNUM		28
178 
179 #define SRDS_MAX_LANES		4
180 #define CONFIG_SYS_FSL_SRDS_1
181 #define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
182 
183 #define CONFIG_SYS_FSL_SFP_VER_3_2
184 #define CONFIG_SYS_FSL_SEC_MON_BE
185 #define CONFIG_SYS_FSL_SEC_BE
186 #define CONFIG_SYS_FSL_SFP_BE
187 #define CONFIG_SYS_FSL_SRK_LE
188 #define CONFIG_KEY_REVOCATION
189 
190 /* SMMU Defintions */
191 #define SMMU_BASE		0x09000000
192 
193 /* Generic Interrupt Controller Definitions */
194 #define GICD_BASE		0x01401000
195 #define GICC_BASE		0x01402000
196 
197 #define CONFIG_SYS_FSL_ERRATUM_A008850
198 #define CONFIG_SYS_FSL_ERRATUM_A009663
199 #define CONFIG_SYS_FSL_ERRATUM_A009929
200 #define CONFIG_SYS_FSL_ERRATUM_A009942
201 #define CONFIG_SYS_FSL_ERRATUM_A009660
202 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
203 #else
204 #error SoC not defined
205 #endif
206 
207 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
208