1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <fsl_ddrc_version.h> 11 12 #ifdef CONFIG_SYS_FSL_DDR4 13 #define CONFIG_SYS_FSL_DDRC_GEN4 14 #else 15 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ 16 #endif 17 18 #ifndef CONFIG_LS1012A 19 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ 20 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 21 #endif 22 23 /* 24 * Reserve secure memory 25 * To be aligned with MMU block size 26 */ 27 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ 28 29 #ifdef CONFIG_LS2080A 30 #define CONFIG_MAX_CPUS 16 31 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 32 #define CONFIG_NUM_DDR_CONTROLLERS 3 33 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ 34 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 35 #define SRDS_MAX_LANES 8 36 #define CONFIG_SYS_FSL_SRDS_1 37 #define CONFIG_SYS_FSL_SRDS_2 38 #define CONFIG_SYS_PAGE_SIZE 0x10000 39 #define CONFIG_SYS_CACHELINE_SIZE 64 40 #ifndef L1_CACHE_BYTES 41 #define L1_CACHE_SHIFT 6 42 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 43 #endif 44 45 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 46 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 47 48 /* DDR */ 49 #define CONFIG_SYS_FSL_DDR_LE 50 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 51 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 52 53 #define CONFIG_SYS_FSL_CCSR_GUR_LE 54 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 55 #define CONFIG_SYS_FSL_ESDHC_LE 56 #define CONFIG_SYS_FSL_IFC_LE 57 #define CONFIG_SYS_FSL_PEX_LUT_LE 58 59 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 60 61 /* Generic Interrupt Controller Definitions */ 62 #define GICD_BASE 0x06000000 63 #define GICR_BASE 0x06100000 64 65 /* SMMU Defintions */ 66 #define SMMU_BASE 0x05000000 /* GR0 Base */ 67 68 /* SFP */ 69 #define CONFIG_SYS_FSL_SFP_VER_3_4 70 #define CONFIG_SYS_FSL_SFP_LE 71 #define CONFIG_SYS_FSL_SRK_LE 72 73 /* SEC */ 74 #define CONFIG_SYS_FSL_SEC_LE 75 #define CONFIG_SYS_FSL_SEC_COMPAT 5 76 77 /* Security Monitor */ 78 #define CONFIG_SYS_FSL_SEC_MON_LE 79 80 /* Secure Boot */ 81 #define CONFIG_ESBC_HDR_LS 82 83 /* DCFG - GUR */ 84 #define CONFIG_SYS_FSL_CCSR_GUR_LE 85 86 /* Cache Coherent Interconnect */ 87 #define CCI_MN_BASE 0x04000000 88 #define CCI_MN_RNF_NODEID_LIST 0x180 89 #define CCI_MN_DVM_DOMAIN_CTL 0x200 90 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 91 92 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 93 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 94 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 95 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 96 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 97 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 98 99 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 100 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 101 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 102 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 103 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 104 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 105 106 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 107 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 108 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 109 110 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 111 112 /* TZ Protection Controller Definitions */ 113 #define TZPC_BASE 0x02200000 114 #define TZPCR0SIZE_BASE (TZPC_BASE) 115 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 116 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 117 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 118 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 119 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 120 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 121 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 122 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 123 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 124 125 #define DCSR_CGACRE5 0x700070914ULL 126 #define EPU_EPCMPR5 0x700060914ULL 127 #define EPU_EPCCR5 0x700060814ULL 128 #define EPU_EPSMCR5 0x700060228ULL 129 #define EPU_EPECR5 0x700060314ULL 130 #define EPU_EPCTR5 0x700060a14ULL 131 #define EPU_EPGCR 0x700060000ULL 132 133 #define CONFIG_SYS_FSL_ERRATUM_A008336 134 #define CONFIG_SYS_FSL_ERRATUM_A008511 135 #define CONFIG_SYS_FSL_ERRATUM_A008514 136 #define CONFIG_SYS_FSL_ERRATUM_A008585 137 #define CONFIG_SYS_FSL_ERRATUM_A008751 138 #define CONFIG_SYS_FSL_ERRATUM_A009635 139 #define CONFIG_SYS_FSL_ERRATUM_A009663 140 #define CONFIG_SYS_FSL_ERRATUM_A009801 141 #define CONFIG_SYS_FSL_ERRATUM_A009803 142 #define CONFIG_SYS_FSL_ERRATUM_A009942 143 #define CONFIG_SYS_FSL_ERRATUM_A010165 144 145 /* ARM A57 CORE ERRATA */ 146 #define CONFIG_ARM_ERRATA_826974 147 #define CONFIG_ARM_ERRATA_828024 148 #define CONFIG_ARM_ERRATA_829520 149 #define CONFIG_ARM_ERRATA_833471 150 151 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 152 #elif defined(CONFIG_LS1043A) 153 #define CONFIG_MAX_CPUS 4 154 #define CONFIG_SYS_CACHELINE_SIZE 64 155 #define CONFIG_SYS_FMAN_V3 156 #define CONFIG_SYS_NUM_FMAN 1 157 #define CONFIG_SYS_NUM_FM1_DTSEC 7 158 #define CONFIG_SYS_NUM_FM1_10GEC 1 159 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 160 #define CONFIG_NUM_DDR_CONTROLLERS 1 161 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 162 #define CONFIG_SYS_FSL_SEC_COMPAT 5 163 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 164 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ 165 #define CONFIG_SYS_FSL_DDR_BE 166 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 167 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 168 169 #define CONFIG_SYS_FSL_CCSR_GUR_BE 170 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 171 #define CONFIG_SYS_FSL_IFC_BE 172 #define CONFIG_SYS_FSL_ESDHC_BE 173 #define CONFIG_SYS_FSL_WDOG_BE 174 #define CONFIG_SYS_FSL_DSPI_BE 175 #define CONFIG_SYS_FSL_QSPI_BE 176 #define CONFIG_SYS_FSL_PEX_LUT_BE 177 178 #define QE_MURAM_SIZE 0x6000UL 179 #define MAX_QE_RISC 1 180 #define QE_NUM_OF_SNUM 28 181 182 #define SRDS_MAX_LANES 4 183 #define CONFIG_SYS_FSL_SRDS_1 184 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 185 186 #define CONFIG_SYS_FSL_SFP_VER_3_2 187 #define CONFIG_SYS_FSL_SEC_MON_BE 188 #define CONFIG_SYS_FSL_SEC_BE 189 #define CONFIG_SYS_FSL_SFP_BE 190 #define CONFIG_SYS_FSL_SRK_LE 191 #define CONFIG_KEY_REVOCATION 192 193 /* SMMU Defintions */ 194 #define SMMU_BASE 0x09000000 195 196 /* Generic Interrupt Controller Definitions */ 197 #define GICD_BASE 0x01401000 198 #define GICC_BASE 0x01402000 199 200 #define CONFIG_SYS_FSL_ERRATUM_A008850 201 #define CONFIG_SYS_FSL_ERRATUM_A009663 202 #define CONFIG_SYS_FSL_ERRATUM_A009929 203 #define CONFIG_SYS_FSL_ERRATUM_A009942 204 #define CONFIG_SYS_FSL_ERRATUM_A009660 205 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 206 #elif defined(CONFIG_LS1012A) 207 #define CONFIG_MAX_CPUS 1 208 #define CONFIG_SYS_CACHELINE_SIZE 64 209 #define CONFIG_NUM_DDR_CONTROLLERS 1 210 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 211 #define CONFIG_SYS_FSL_SEC_COMPAT 5 212 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 213 214 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 215 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ 216 217 #define GICD_BASE 0x01401000 218 #define GICC_BASE 0x01402000 219 220 #define CONFIG_SYS_FSL_CCSR_GUR_BE 221 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 222 #define CONFIG_SYS_FSL_ESDHC_BE 223 #define CONFIG_SYS_FSL_WDOG_BE 224 #define CONFIG_SYS_FSL_DSPI_BE 225 #define CONFIG_SYS_FSL_QSPI_BE 226 #define CONFIG_SYS_FSL_PEX_LUT_BE 227 228 #define SRDS_MAX_LANES 4 229 #define CONFIG_SYS_FSL_SRDS_1 230 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 231 #define CONFIG_SYS_FSL_SEC_BE 232 #else 233 #error SoC not defined 234 #endif 235 236 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 237