1 /*
2  * Copyright 2015, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
9 
10 #include <fsl_ddrc_version.h>
11 
12 #ifdef CONFIG_SYS_FSL_DDR4
13 #define CONFIG_SYS_FSL_DDRC_GEN4
14 #else
15 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
16 #endif
17 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
18 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
19 
20 #if defined(CONFIG_LS2085A)
21 #define CONFIG_MAX_CPUS				16
22 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
23 #define CONFIG_NUM_DDR_CONTROLLERS		3
24 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
25 #define	SRDS_MAX_LANES	8
26 #define CONFIG_SYS_FSL_SRDS_1
27 #define CONFIG_SYS_FSL_SRDS_2
28 #define CONFIG_SYS_PAGE_SIZE		0x10000
29 #define CONFIG_SYS_CACHELINE_SIZE	64
30 #ifndef L1_CACHE_BYTES
31 #define L1_CACHE_SHIFT		6
32 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
33 #endif
34 
35 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
36 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00200000	/* 2M */
37 
38 /* DDR */
39 #define CONFIG_SYS_FSL_DDR_LE
40 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
41 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
42 
43 #define CONFIG_SYS_FSL_CCSR_GUR_LE
44 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
45 #define CONFIG_SYS_FSL_ESDHC_LE
46 #define CONFIG_SYS_FSL_IFC_LE
47 
48 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
49 
50 /* Generic Interrupt Controller Definitions */
51 #define GICD_BASE			0x06000000
52 #define GICR_BASE			0x06100000
53 
54 /* SMMU Defintions */
55 #define SMMU_BASE			0x05000000 /* GR0 Base */
56 
57 /* Cache Coherent Interconnect */
58 #define CCI_MN_BASE			0x04000000
59 #define CCI_MN_RNF_NODEID_LIST		0x180
60 #define CCI_MN_DVM_DOMAIN_CTL		0x200
61 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
62 
63 #define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
64 #define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
65 #define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
66 #define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
67 #define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
68 #define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
69 
70 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
71 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
72 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
73 
74 /* TZ Protection Controller Definitions */
75 #define TZPC_BASE				0x02200000
76 #define TZPCR0SIZE_BASE				(TZPC_BASE)
77 #define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
78 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
79 #define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
80 #define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
81 #define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
82 #define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
83 #define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
84 #define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
85 #define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
86 
87 #define CONFIG_SYS_FSL_ERRATUM_A008336
88 #define CONFIG_SYS_FSL_ERRATUM_A008511
89 #define CONFIG_SYS_FSL_ERRATUM_A008514
90 #define CONFIG_SYS_FSL_ERRATUM_A008585
91 #define CONFIG_SYS_FSL_ERRATUM_A008751
92 #elif defined(CONFIG_LS1043A)
93 #define CONFIG_MAX_CPUS				4
94 #define CONFIG_SYS_CACHELINE_SIZE		64
95 #define CONFIG_SYS_FMAN_V3
96 #define CONFIG_SYS_NUM_FMAN			1
97 #define CONFIG_SYS_NUM_FM1_DTSEC		7
98 #define CONFIG_SYS_NUM_FM1_10GEC		1
99 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		4
100 #define CONFIG_NUM_DDR_CONTROLLERS		1
101 #define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
102 #define CONFIG_SYS_FSL_SEC_COMPAT		5
103 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
104 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
105 #define CONFIG_SYS_FSL_DDR_BE
106 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
107 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
108 
109 #define CONFIG_SYS_FSL_CCSR_GUR_BE
110 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
111 #define CONFIG_SYS_FSL_IFC_BE
112 #define CONFIG_SYS_FSL_ESDHC_BE
113 #define CONFIG_SYS_FSL_WDOG_BE
114 #define CONFIG_SYS_FSL_DSPI_BE
115 #define CONFIG_SYS_FSL_QSPI_BE
116 
117 #define QE_MURAM_SIZE		0x6000UL
118 #define MAX_QE_RISC		1
119 #define QE_NUM_OF_SNUM		28
120 
121 #define SRDS_MAX_LANES		4
122 #define CONFIG_SYS_FSL_SRDS_1
123 #define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
124 
125 #define CONFIG_SYS_FSL_SFP_VER_3_2
126 #define CONFIG_SYS_FSL_SNVS_LE
127 #define CONFIG_SYS_FSL_SEC_LE
128 #define CONFIG_SYS_FSL_SFP_BE
129 #define CONFIG_SYS_FSL_SRK_LE
130 #define CONFIG_KEY_REVOCATION
131 
132 /* SMMU Defintions */
133 #define SMMU_BASE		0x09000000
134 
135 /* Generic Interrupt Controller Definitions */
136 #define GICD_BASE		0x01401000
137 #define GICC_BASE		0x01402000
138 
139 #else
140 #error SoC not defined
141 #endif
142 
143 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
144