1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 14 15 /* 16 * Reserve secure memory 17 * To be aligned with MMU block size 18 */ 19 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ 20 21 #ifdef CONFIG_LS2080A 22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 23 #define SRDS_MAX_LANES 8 24 #define CONFIG_SYS_PAGE_SIZE 0x10000 25 #ifndef L1_CACHE_BYTES 26 #define L1_CACHE_SHIFT 6 27 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 28 #define CONFIG_FSL_TZASC_400 29 #endif 30 31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 32 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 33 34 /* DDR */ 35 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 36 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 37 38 #define CONFIG_SYS_FSL_CCSR_GUR_LE 39 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 40 #define CONFIG_SYS_FSL_ESDHC_LE 41 #define CONFIG_SYS_FSL_IFC_LE 42 #define CONFIG_SYS_FSL_PEX_LUT_LE 43 44 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 45 46 /* Generic Interrupt Controller Definitions */ 47 #define GICD_BASE 0x06000000 48 #define GICR_BASE 0x06100000 49 50 /* SMMU Defintions */ 51 #define SMMU_BASE 0x05000000 /* GR0 Base */ 52 53 /* SFP */ 54 #define CONFIG_SYS_FSL_SFP_VER_3_4 55 #define CONFIG_SYS_FSL_SFP_LE 56 #define CONFIG_SYS_FSL_SRK_LE 57 58 /* Security Monitor */ 59 #define CONFIG_SYS_FSL_SEC_MON_LE 60 61 /* Secure Boot */ 62 #define CONFIG_ESBC_HDR_LS 63 64 /* DCFG - GUR */ 65 #define CONFIG_SYS_FSL_CCSR_GUR_LE 66 67 /* Cache Coherent Interconnect */ 68 #define CCI_MN_BASE 0x04000000 69 #define CCI_MN_RNF_NODEID_LIST 0x180 70 #define CCI_MN_DVM_DOMAIN_CTL 0x200 71 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 72 73 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 74 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 75 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 76 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 77 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 78 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 79 80 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 81 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 82 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 83 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 84 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 85 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 86 87 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 88 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 89 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 90 91 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 92 93 /* TZ Protection Controller Definitions */ 94 #define TZPC_BASE 0x02200000 95 #define TZPCR0SIZE_BASE (TZPC_BASE) 96 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 97 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 98 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 99 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 100 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 101 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 102 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 103 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 104 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 105 106 #define DCSR_CGACRE5 0x700070914ULL 107 #define EPU_EPCMPR5 0x700060914ULL 108 #define EPU_EPCCR5 0x700060814ULL 109 #define EPU_EPSMCR5 0x700060228ULL 110 #define EPU_EPECR5 0x700060314ULL 111 #define EPU_EPCTR5 0x700060a14ULL 112 #define EPU_EPGCR 0x700060000ULL 113 114 #define CONFIG_SYS_FSL_ERRATUM_A008751 115 116 /* ARM A57 CORE ERRATA */ 117 #define CONFIG_ARM_ERRATA_826974 118 #define CONFIG_ARM_ERRATA_828024 119 #define CONFIG_ARM_ERRATA_829520 120 #define CONFIG_ARM_ERRATA_833471 121 122 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 123 #elif defined(CONFIG_FSL_LSCH2) 124 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 125 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 126 127 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 128 #define CONFIG_SYS_FSL_ESDHC_BE 129 #define CONFIG_SYS_FSL_WDOG_BE 130 #define CONFIG_SYS_FSL_DSPI_BE 131 #define CONFIG_SYS_FSL_QSPI_BE 132 #define CONFIG_SYS_FSL_CCSR_GUR_BE 133 #define CONFIG_SYS_FSL_PEX_LUT_BE 134 135 /* SoC related */ 136 #ifdef CONFIG_LS1043A 137 #define CONFIG_SYS_FMAN_V3 138 #define CONFIG_SYS_NUM_FMAN 1 139 #define CONFIG_SYS_NUM_FM1_DTSEC 7 140 #define CONFIG_SYS_NUM_FM1_10GEC 1 141 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 142 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 143 144 #define QE_MURAM_SIZE 0x6000UL 145 #define MAX_QE_RISC 1 146 #define QE_NUM_OF_SNUM 28 147 148 #define CONFIG_SYS_FSL_IFC_BE 149 #define CONFIG_SYS_FSL_SFP_VER_3_2 150 #define CONFIG_SYS_FSL_SEC_MON_BE 151 #define CONFIG_SYS_FSL_SFP_BE 152 #define CONFIG_SYS_FSL_SRK_LE 153 #define CONFIG_KEY_REVOCATION 154 155 /* SMMU Defintions */ 156 #define SMMU_BASE 0x09000000 157 158 /* Generic Interrupt Controller Definitions */ 159 #define GICD_BASE 0x01401000 160 #define GICC_BASE 0x01402000 161 162 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 163 164 #elif defined(CONFIG_ARCH_LS1012A) 165 #define GICD_BASE 0x01401000 166 #define GICC_BASE 0x01402000 167 168 #elif defined(CONFIG_ARCH_LS1046A) 169 #define CONFIG_SYS_FMAN_V3 170 #define CONFIG_SYS_NUM_FMAN 1 171 #define CONFIG_SYS_NUM_FM1_DTSEC 8 172 #define CONFIG_SYS_NUM_FM1_10GEC 2 173 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 174 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 175 176 #define CONFIG_SYS_FSL_IFC_BE 177 #define CONFIG_SYS_FSL_SFP_VER_3_2 178 #define CONFIG_SYS_FSL_SNVS_LE 179 #define CONFIG_SYS_FSL_SFP_BE 180 #define CONFIG_SYS_FSL_SRK_LE 181 #define CONFIG_KEY_REVOCATION 182 183 /* SMMU Defintions */ 184 #define SMMU_BASE 0x09000000 185 186 /* Generic Interrupt Controller Definitions */ 187 #define GICD_BASE 0x01410000 188 #define GICC_BASE 0x01420000 189 190 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 191 192 #else 193 #error SoC not defined 194 #endif 195 #endif 196 197 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 198