1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 14 15 /* 16 * Reserve secure memory 17 * To be aligned with MMU block size 18 */ 19 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ 20 21 #ifdef CONFIG_LS2080A 22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 23 #define SRDS_MAX_LANES 8 24 #define CONFIG_SYS_PAGE_SIZE 0x10000 25 #ifndef L1_CACHE_BYTES 26 #define L1_CACHE_SHIFT 6 27 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 28 #define CONFIG_FSL_TZASC_400 29 #endif 30 31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 32 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 33 34 /* DDR */ 35 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 36 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 37 38 #define CONFIG_SYS_FSL_CCSR_GUR_LE 39 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 40 #define CONFIG_SYS_FSL_ESDHC_LE 41 #define CONFIG_SYS_FSL_IFC_LE 42 #define CONFIG_SYS_FSL_PEX_LUT_LE 43 44 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 45 46 /* Generic Interrupt Controller Definitions */ 47 #define GICD_BASE 0x06000000 48 #define GICR_BASE 0x06100000 49 50 /* SMMU Defintions */ 51 #define SMMU_BASE 0x05000000 /* GR0 Base */ 52 53 /* SFP */ 54 #define CONFIG_SYS_FSL_SFP_VER_3_4 55 #define CONFIG_SYS_FSL_SFP_LE 56 #define CONFIG_SYS_FSL_SRK_LE 57 58 /* SEC */ 59 #define CONFIG_SYS_FSL_SEC_LE 60 #define CONFIG_SYS_FSL_SEC_COMPAT 5 61 62 /* Security Monitor */ 63 #define CONFIG_SYS_FSL_SEC_MON_LE 64 65 /* Secure Boot */ 66 #define CONFIG_ESBC_HDR_LS 67 68 /* DCFG - GUR */ 69 #define CONFIG_SYS_FSL_CCSR_GUR_LE 70 71 /* Cache Coherent Interconnect */ 72 #define CCI_MN_BASE 0x04000000 73 #define CCI_MN_RNF_NODEID_LIST 0x180 74 #define CCI_MN_DVM_DOMAIN_CTL 0x200 75 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 76 77 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 78 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 79 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 80 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 81 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 82 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 83 84 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 85 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 86 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 87 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 88 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 89 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 90 91 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 92 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 93 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 94 95 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 96 97 /* TZ Protection Controller Definitions */ 98 #define TZPC_BASE 0x02200000 99 #define TZPCR0SIZE_BASE (TZPC_BASE) 100 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 101 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 102 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 103 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 104 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 105 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 106 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 107 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 108 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 109 110 #define DCSR_CGACRE5 0x700070914ULL 111 #define EPU_EPCMPR5 0x700060914ULL 112 #define EPU_EPCCR5 0x700060814ULL 113 #define EPU_EPSMCR5 0x700060228ULL 114 #define EPU_EPECR5 0x700060314ULL 115 #define EPU_EPCTR5 0x700060a14ULL 116 #define EPU_EPGCR 0x700060000ULL 117 118 #define CONFIG_SYS_FSL_ERRATUM_A008336 119 #define CONFIG_SYS_FSL_ERRATUM_A008511 120 #define CONFIG_SYS_FSL_ERRATUM_A008514 121 #define CONFIG_SYS_FSL_ERRATUM_A008585 122 #define CONFIG_SYS_FSL_ERRATUM_A008751 123 #define CONFIG_SYS_FSL_ERRATUM_A009635 124 #define CONFIG_SYS_FSL_ERRATUM_A009663 125 #define CONFIG_SYS_FSL_ERRATUM_A009801 126 #define CONFIG_SYS_FSL_ERRATUM_A009803 127 #define CONFIG_SYS_FSL_ERRATUM_A009942 128 #define CONFIG_SYS_FSL_ERRATUM_A010165 129 130 /* ARM A57 CORE ERRATA */ 131 #define CONFIG_ARM_ERRATA_826974 132 #define CONFIG_ARM_ERRATA_828024 133 #define CONFIG_ARM_ERRATA_829520 134 #define CONFIG_ARM_ERRATA_833471 135 136 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 137 #elif defined(CONFIG_FSL_LSCH2) 138 #define CONFIG_SYS_FSL_SEC_COMPAT 5 139 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 140 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 141 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 142 143 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 144 #define CONFIG_SYS_FSL_ESDHC_BE 145 #define CONFIG_SYS_FSL_WDOG_BE 146 #define CONFIG_SYS_FSL_DSPI_BE 147 #define CONFIG_SYS_FSL_QSPI_BE 148 #define CONFIG_SYS_FSL_CCSR_GUR_BE 149 #define CONFIG_SYS_FSL_PEX_LUT_BE 150 #define CONFIG_SYS_FSL_SEC_BE 151 152 /* SoC related */ 153 #ifdef CONFIG_LS1043A 154 #define CONFIG_SYS_FMAN_V3 155 #define CONFIG_SYS_NUM_FMAN 1 156 #define CONFIG_SYS_NUM_FM1_DTSEC 7 157 #define CONFIG_SYS_NUM_FM1_10GEC 1 158 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 159 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 160 161 #define QE_MURAM_SIZE 0x6000UL 162 #define MAX_QE_RISC 1 163 #define QE_NUM_OF_SNUM 28 164 165 #define CONFIG_SYS_FSL_IFC_BE 166 #define CONFIG_SYS_FSL_SFP_VER_3_2 167 #define CONFIG_SYS_FSL_SEC_MON_BE 168 #define CONFIG_SYS_FSL_SFP_BE 169 #define CONFIG_SYS_FSL_SRK_LE 170 #define CONFIG_KEY_REVOCATION 171 172 /* SMMU Defintions */ 173 #define SMMU_BASE 0x09000000 174 175 /* Generic Interrupt Controller Definitions */ 176 #define GICD_BASE 0x01401000 177 #define GICC_BASE 0x01402000 178 179 #define CONFIG_SYS_FSL_ERRATUM_A008850 180 #define CONFIG_SYS_FSL_ERRATUM_A009663 181 #define CONFIG_SYS_FSL_ERRATUM_A009929 182 #define CONFIG_SYS_FSL_ERRATUM_A009942 183 #define CONFIG_SYS_FSL_ERRATUM_A009660 184 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 185 #elif defined(CONFIG_ARCH_LS1012A) 186 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 187 188 #define GICD_BASE 0x01401000 189 #define GICC_BASE 0x01402000 190 #elif defined(CONFIG_ARCH_LS1046A) 191 #define CONFIG_SYS_FMAN_V3 192 #define CONFIG_SYS_NUM_FMAN 1 193 #define CONFIG_SYS_NUM_FM1_DTSEC 8 194 #define CONFIG_SYS_NUM_FM1_10GEC 2 195 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 196 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 197 198 #define CONFIG_SYS_FSL_IFC_BE 199 #define CONFIG_SYS_FSL_SFP_VER_3_2 200 #define CONFIG_SYS_FSL_SNVS_LE 201 #define CONFIG_SYS_FSL_SFP_BE 202 #define CONFIG_SYS_FSL_SRK_LE 203 #define CONFIG_KEY_REVOCATION 204 205 /* SMMU Defintions */ 206 #define SMMU_BASE 0x09000000 207 208 /* Generic Interrupt Controller Definitions */ 209 #define GICD_BASE 0x01410000 210 #define GICC_BASE 0x01420000 211 212 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 213 214 #define CONFIG_SYS_FSL_ERRATUM_A008511 215 #define CONFIG_SYS_FSL_ERRATUM_A009801 216 #define CONFIG_SYS_FSL_ERRATUM_A009803 217 #define CONFIG_SYS_FSL_ERRATUM_A009942 218 #define CONFIG_SYS_FSL_ERRATUM_A010165 219 #else 220 #error SoC not defined 221 #endif 222 #endif 223 224 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 225