1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 14 15 /* 16 * Reserve secure memory 17 * To be aligned with MMU block size 18 */ 19 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ 20 21 #ifdef CONFIG_LS2080A 22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 23 #define SRDS_MAX_LANES 8 24 #define CONFIG_SYS_PAGE_SIZE 0x10000 25 #ifndef L1_CACHE_BYTES 26 #define L1_CACHE_SHIFT 6 27 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 28 #define CONFIG_FSL_TZASC_400 29 #endif 30 31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 34 35 /* DDR */ 36 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 37 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 38 39 #define CONFIG_SYS_FSL_CCSR_GUR_LE 40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 41 #define CONFIG_SYS_FSL_ESDHC_LE 42 #define CONFIG_SYS_FSL_IFC_LE 43 #define CONFIG_SYS_FSL_PEX_LUT_LE 44 45 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 46 47 /* Generic Interrupt Controller Definitions */ 48 #define GICD_BASE 0x06000000 49 #define GICR_BASE 0x06100000 50 51 /* SMMU Defintions */ 52 #define SMMU_BASE 0x05000000 /* GR0 Base */ 53 54 /* SFP */ 55 #define CONFIG_SYS_FSL_SFP_VER_3_4 56 #define CONFIG_SYS_FSL_SFP_LE 57 #define CONFIG_SYS_FSL_SRK_LE 58 59 /* Security Monitor */ 60 #define CONFIG_SYS_FSL_SEC_MON_LE 61 62 /* Secure Boot */ 63 #define CONFIG_ESBC_HDR_LS 64 65 /* DCFG - GUR */ 66 #define CONFIG_SYS_FSL_CCSR_GUR_LE 67 68 /* Cache Coherent Interconnect */ 69 #define CCI_MN_BASE 0x04000000 70 #define CCI_MN_RNF_NODEID_LIST 0x180 71 #define CCI_MN_DVM_DOMAIN_CTL 0x200 72 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 73 74 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 75 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 76 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 77 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 78 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 79 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 80 81 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 82 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 83 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 84 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 85 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 86 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 87 88 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 90 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 91 92 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 93 94 /* TZ Protection Controller Definitions */ 95 #define TZPC_BASE 0x02200000 96 #define TZPCR0SIZE_BASE (TZPC_BASE) 97 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 98 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 99 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 100 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 101 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 102 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 103 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 104 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 105 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 106 107 #define DCSR_CGACRE5 0x700070914ULL 108 #define EPU_EPCMPR5 0x700060914ULL 109 #define EPU_EPCCR5 0x700060814ULL 110 #define EPU_EPSMCR5 0x700060228ULL 111 #define EPU_EPECR5 0x700060314ULL 112 #define EPU_EPCTR5 0x700060a14ULL 113 #define EPU_EPGCR 0x700060000ULL 114 115 #define CONFIG_SYS_FSL_ERRATUM_A008751 116 117 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 118 #elif defined(CONFIG_FSL_LSCH2) 119 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 120 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 121 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 122 123 #define DCSR_DCFG_SBEESR2 0x20140534 124 #define DCSR_DCFG_MBEESR2 0x20140544 125 126 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 127 #define CONFIG_SYS_FSL_ESDHC_BE 128 #define CONFIG_SYS_FSL_WDOG_BE 129 #define CONFIG_SYS_FSL_DSPI_BE 130 #define CONFIG_SYS_FSL_QSPI_BE 131 #define CONFIG_SYS_FSL_CCSR_GUR_BE 132 #define CONFIG_SYS_FSL_PEX_LUT_BE 133 134 /* SoC related */ 135 #ifdef CONFIG_LS1043A 136 #define CONFIG_SYS_FMAN_V3 137 #define CONFIG_SYS_NUM_FMAN 1 138 #define CONFIG_SYS_NUM_FM1_DTSEC 7 139 #define CONFIG_SYS_NUM_FM1_10GEC 1 140 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 141 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 142 143 #define QE_MURAM_SIZE 0x6000UL 144 #define MAX_QE_RISC 1 145 #define QE_NUM_OF_SNUM 28 146 147 #define CONFIG_SYS_FSL_IFC_BE 148 #define CONFIG_SYS_FSL_SFP_VER_3_2 149 #define CONFIG_SYS_FSL_SEC_MON_BE 150 #define CONFIG_SYS_FSL_SFP_BE 151 #define CONFIG_SYS_FSL_SRK_LE 152 #define CONFIG_KEY_REVOCATION 153 154 /* SMMU Defintions */ 155 #define SMMU_BASE 0x09000000 156 157 /* Generic Interrupt Controller Definitions */ 158 #define GICD_BASE 0x01401000 159 #define GICC_BASE 0x01402000 160 #define GICH_BASE 0x01404000 161 #define GICV_BASE 0x01406000 162 #define GICD_SIZE 0x1000 163 #define GICC_SIZE 0x2000 164 #define GICH_SIZE 0x2000 165 #define GICV_SIZE 0x2000 166 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 167 #define GICD_BASE_64K 0x01410000 168 #define GICC_BASE_64K 0x01420000 169 #define GICH_BASE_64K 0x01440000 170 #define GICV_BASE_64K 0x01460000 171 #define GICD_SIZE_64K 0x10000 172 #define GICC_SIZE_64K 0x20000 173 #define GICH_SIZE_64K 0x20000 174 #define GICV_SIZE_64K 0x20000 175 #endif 176 177 #define DCFG_CCSR_SVR 0x1ee00a4 178 #define REV1_0 0x10 179 #define REV1_1 0x11 180 #define GIC_ADDR_BIT 31 181 #define SCFG_GIC400_ALIGN 0x1570188 182 183 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 184 185 #elif defined(CONFIG_ARCH_LS1012A) 186 #define GICD_BASE 0x01401000 187 #define GICC_BASE 0x01402000 188 189 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 190 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 191 192 #elif defined(CONFIG_ARCH_LS1046A) 193 #define CONFIG_SYS_FMAN_V3 194 #define CONFIG_SYS_NUM_FMAN 1 195 #define CONFIG_SYS_NUM_FM1_DTSEC 8 196 #define CONFIG_SYS_NUM_FM1_10GEC 2 197 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 198 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 199 200 #define CONFIG_SYS_FSL_IFC_BE 201 #define CONFIG_SYS_FSL_SFP_VER_3_2 202 #define CONFIG_SYS_FSL_SNVS_LE 203 #define CONFIG_SYS_FSL_SFP_BE 204 #define CONFIG_SYS_FSL_SRK_LE 205 #define CONFIG_KEY_REVOCATION 206 207 /* SMMU Defintions */ 208 #define SMMU_BASE 0x09000000 209 210 /* Generic Interrupt Controller Definitions */ 211 #define GICD_BASE 0x01410000 212 #define GICC_BASE 0x01420000 213 214 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 215 216 #else 217 #error SoC not defined 218 #endif 219 #endif 220 221 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 222