1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <linux/kconfig.h> 11 #include <fsl_ddrc_version.h> 12 13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 14 15 /* 16 * Reserve secure memory 17 * To be aligned with MMU block size 18 */ 19 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ 20 21 #ifdef CONFIG_LS2080A 22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 23 #define SRDS_MAX_LANES 8 24 #define CONFIG_SYS_PAGE_SIZE 0x10000 25 #ifndef L1_CACHE_BYTES 26 #define L1_CACHE_SHIFT 6 27 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 28 #endif 29 30 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 31 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 32 33 /* DDR */ 34 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 35 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 36 37 #define CONFIG_SYS_FSL_CCSR_GUR_LE 38 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 39 #define CONFIG_SYS_FSL_ESDHC_LE 40 #define CONFIG_SYS_FSL_IFC_LE 41 #define CONFIG_SYS_FSL_PEX_LUT_LE 42 43 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 44 45 /* Generic Interrupt Controller Definitions */ 46 #define GICD_BASE 0x06000000 47 #define GICR_BASE 0x06100000 48 49 /* SMMU Defintions */ 50 #define SMMU_BASE 0x05000000 /* GR0 Base */ 51 52 /* SFP */ 53 #define CONFIG_SYS_FSL_SFP_VER_3_4 54 #define CONFIG_SYS_FSL_SFP_LE 55 #define CONFIG_SYS_FSL_SRK_LE 56 57 /* SEC */ 58 #define CONFIG_SYS_FSL_SEC_LE 59 #define CONFIG_SYS_FSL_SEC_COMPAT 5 60 61 /* Security Monitor */ 62 #define CONFIG_SYS_FSL_SEC_MON_LE 63 64 /* Secure Boot */ 65 #define CONFIG_ESBC_HDR_LS 66 67 /* DCFG - GUR */ 68 #define CONFIG_SYS_FSL_CCSR_GUR_LE 69 70 /* Cache Coherent Interconnect */ 71 #define CCI_MN_BASE 0x04000000 72 #define CCI_MN_RNF_NODEID_LIST 0x180 73 #define CCI_MN_DVM_DOMAIN_CTL 0x200 74 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 75 76 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 77 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 78 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 79 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 80 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 81 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 82 83 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 84 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 85 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 86 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 87 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 88 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 89 90 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 91 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 92 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 93 94 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 95 96 /* TZ Protection Controller Definitions */ 97 #define TZPC_BASE 0x02200000 98 #define TZPCR0SIZE_BASE (TZPC_BASE) 99 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 100 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 101 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 102 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 103 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 104 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 105 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 106 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 107 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 108 109 #define DCSR_CGACRE5 0x700070914ULL 110 #define EPU_EPCMPR5 0x700060914ULL 111 #define EPU_EPCCR5 0x700060814ULL 112 #define EPU_EPSMCR5 0x700060228ULL 113 #define EPU_EPECR5 0x700060314ULL 114 #define EPU_EPCTR5 0x700060a14ULL 115 #define EPU_EPGCR 0x700060000ULL 116 117 #define CONFIG_SYS_FSL_ERRATUM_A008336 118 #define CONFIG_SYS_FSL_ERRATUM_A008511 119 #define CONFIG_SYS_FSL_ERRATUM_A008514 120 #define CONFIG_SYS_FSL_ERRATUM_A008585 121 #define CONFIG_SYS_FSL_ERRATUM_A008751 122 #define CONFIG_SYS_FSL_ERRATUM_A009635 123 #define CONFIG_SYS_FSL_ERRATUM_A009663 124 #define CONFIG_SYS_FSL_ERRATUM_A009801 125 #define CONFIG_SYS_FSL_ERRATUM_A009803 126 #define CONFIG_SYS_FSL_ERRATUM_A009942 127 #define CONFIG_SYS_FSL_ERRATUM_A010165 128 129 /* ARM A57 CORE ERRATA */ 130 #define CONFIG_ARM_ERRATA_826974 131 #define CONFIG_ARM_ERRATA_828024 132 #define CONFIG_ARM_ERRATA_829520 133 #define CONFIG_ARM_ERRATA_833471 134 135 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 136 #elif defined(CONFIG_FSL_LSCH2) 137 #define CONFIG_SYS_FSL_SEC_COMPAT 5 138 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 139 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 140 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 141 142 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 143 #define CONFIG_SYS_FSL_ESDHC_BE 144 #define CONFIG_SYS_FSL_WDOG_BE 145 #define CONFIG_SYS_FSL_DSPI_BE 146 #define CONFIG_SYS_FSL_QSPI_BE 147 #define CONFIG_SYS_FSL_CCSR_GUR_BE 148 #define CONFIG_SYS_FSL_PEX_LUT_BE 149 #define CONFIG_SYS_FSL_SEC_BE 150 151 /* SoC related */ 152 #ifdef CONFIG_LS1043A 153 #define CONFIG_SYS_FMAN_V3 154 #define CONFIG_SYS_NUM_FMAN 1 155 #define CONFIG_SYS_NUM_FM1_DTSEC 7 156 #define CONFIG_SYS_NUM_FM1_10GEC 1 157 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 158 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 159 160 #define QE_MURAM_SIZE 0x6000UL 161 #define MAX_QE_RISC 1 162 #define QE_NUM_OF_SNUM 28 163 164 #define CONFIG_SYS_FSL_IFC_BE 165 #define CONFIG_SYS_FSL_SFP_VER_3_2 166 #define CONFIG_SYS_FSL_SEC_MON_BE 167 #define CONFIG_SYS_FSL_SFP_BE 168 #define CONFIG_SYS_FSL_SRK_LE 169 #define CONFIG_KEY_REVOCATION 170 171 /* SMMU Defintions */ 172 #define SMMU_BASE 0x09000000 173 174 /* Generic Interrupt Controller Definitions */ 175 #define GICD_BASE 0x01401000 176 #define GICC_BASE 0x01402000 177 178 #define CONFIG_SYS_FSL_ERRATUM_A008850 179 #define CONFIG_SYS_FSL_ERRATUM_A009663 180 #define CONFIG_SYS_FSL_ERRATUM_A009929 181 #define CONFIG_SYS_FSL_ERRATUM_A009942 182 #define CONFIG_SYS_FSL_ERRATUM_A009660 183 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 184 #elif defined(CONFIG_ARCH_LS1012A) 185 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 186 187 #define GICD_BASE 0x01401000 188 #define GICC_BASE 0x01402000 189 #elif defined(CONFIG_ARCH_LS1046A) 190 #define CONFIG_SYS_FMAN_V3 191 #define CONFIG_SYS_NUM_FMAN 1 192 #define CONFIG_SYS_NUM_FM1_DTSEC 8 193 #define CONFIG_SYS_NUM_FM1_10GEC 2 194 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 195 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 196 197 #define CONFIG_SYS_FSL_IFC_BE 198 #define CONFIG_SYS_FSL_SFP_VER_3_2 199 #define CONFIG_SYS_FSL_SNVS_LE 200 #define CONFIG_SYS_FSL_SFP_BE 201 #define CONFIG_SYS_FSL_SRK_LE 202 #define CONFIG_KEY_REVOCATION 203 204 /* SMMU Defintions */ 205 #define SMMU_BASE 0x09000000 206 207 /* Generic Interrupt Controller Definitions */ 208 #define GICD_BASE 0x01410000 209 #define GICC_BASE 0x01420000 210 211 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 212 213 #define CONFIG_SYS_FSL_ERRATUM_A008511 214 #define CONFIG_SYS_FSL_ERRATUM_A009801 215 #define CONFIG_SYS_FSL_ERRATUM_A009803 216 #define CONFIG_SYS_FSL_ERRATUM_A009942 217 #define CONFIG_SYS_FSL_ERRATUM_A010165 218 #else 219 #error SoC not defined 220 #endif 221 #endif 222 223 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 224