1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <fsl_ddrc_version.h> 11 12 #ifdef CONFIG_SYS_FSL_DDR4 13 #define CONFIG_SYS_FSL_DDRC_GEN4 14 #else 15 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ 16 #endif 17 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ 18 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 19 20 /* 21 * Reserve secure memory 22 * To be aligned with MMU block size 23 */ 24 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ 25 26 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 27 #define CONFIG_MAX_CPUS 16 28 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 29 #ifdef CONFIG_LS2080A 30 #define CONFIG_NUM_DDR_CONTROLLERS 2 31 #endif 32 #ifdef CONFIG_LS2085A 33 #define CONFIG_NUM_DDR_CONTROLLERS 3 34 #define CONFIG_SYS_FSL_HAS_DP_DDR 35 #endif 36 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 37 #define SRDS_MAX_LANES 8 38 #define CONFIG_SYS_FSL_SRDS_1 39 #define CONFIG_SYS_FSL_SRDS_2 40 #define CONFIG_SYS_PAGE_SIZE 0x10000 41 #define CONFIG_SYS_CACHELINE_SIZE 64 42 #ifndef L1_CACHE_BYTES 43 #define L1_CACHE_SHIFT 6 44 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 45 #endif 46 47 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 48 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 49 50 /* DDR */ 51 #define CONFIG_SYS_FSL_DDR_LE 52 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 53 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 54 55 #define CONFIG_SYS_FSL_CCSR_GUR_LE 56 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 57 #define CONFIG_SYS_FSL_ESDHC_LE 58 #define CONFIG_SYS_FSL_IFC_LE 59 #define CONFIG_SYS_FSL_PEX_LUT_LE 60 61 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 62 63 /* Generic Interrupt Controller Definitions */ 64 #define GICD_BASE 0x06000000 65 #define GICR_BASE 0x06100000 66 67 /* SMMU Defintions */ 68 #define SMMU_BASE 0x05000000 /* GR0 Base */ 69 70 /* Cache Coherent Interconnect */ 71 #define CCI_MN_BASE 0x04000000 72 #define CCI_MN_RNF_NODEID_LIST 0x180 73 #define CCI_MN_DVM_DOMAIN_CTL 0x200 74 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 75 76 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 77 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 78 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 79 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 80 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 81 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 82 83 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 84 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 85 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 86 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 87 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 88 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 89 90 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 91 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 92 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 93 94 /* TZ Protection Controller Definitions */ 95 #define TZPC_BASE 0x02200000 96 #define TZPCR0SIZE_BASE (TZPC_BASE) 97 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 98 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 99 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 100 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 101 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 102 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 103 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 104 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 105 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 106 107 #define DCSR_CGACRE5 0x700070914ULL 108 #define EPU_EPCMPR5 0x700060914ULL 109 #define EPU_EPCCR5 0x700060814ULL 110 #define EPU_EPSMCR5 0x700060228ULL 111 #define EPU_EPECR5 0x700060314ULL 112 #define EPU_EPCTR5 0x700060a14ULL 113 #define EPU_EPGCR 0x700060000ULL 114 115 #define CONFIG_SYS_FSL_ERRATUM_A008336 116 #define CONFIG_SYS_FSL_ERRATUM_A008511 117 #define CONFIG_SYS_FSL_ERRATUM_A008514 118 #define CONFIG_SYS_FSL_ERRATUM_A008585 119 #define CONFIG_SYS_FSL_ERRATUM_A008751 120 #define CONFIG_SYS_FSL_ERRATUM_A009635 121 #define CONFIG_SYS_FSL_ERRATUM_A009663 122 #define CONFIG_SYS_FSL_ERRATUM_A009942 123 124 /* ARM A57 CORE ERRATA */ 125 #define CONFIG_ARM_ERRATA_826974 126 #define CONFIG_ARM_ERRATA_828024 127 #define CONFIG_ARM_ERRATA_829520 128 #define CONFIG_ARM_ERRATA_833471 129 130 #elif defined(CONFIG_LS1043A) 131 #define CONFIG_MAX_CPUS 4 132 #define CONFIG_SYS_CACHELINE_SIZE 64 133 #define CONFIG_SYS_FMAN_V3 134 #define CONFIG_SYS_NUM_FMAN 1 135 #define CONFIG_SYS_NUM_FM1_DTSEC 7 136 #define CONFIG_SYS_NUM_FM1_10GEC 1 137 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 138 #define CONFIG_NUM_DDR_CONTROLLERS 1 139 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 140 #define CONFIG_SYS_FSL_SEC_COMPAT 5 141 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 142 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ 143 #define CONFIG_SYS_FSL_DDR_BE 144 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 145 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 146 147 #define CONFIG_SYS_FSL_CCSR_GUR_BE 148 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 149 #define CONFIG_SYS_FSL_IFC_BE 150 #define CONFIG_SYS_FSL_ESDHC_BE 151 #define CONFIG_SYS_FSL_WDOG_BE 152 #define CONFIG_SYS_FSL_DSPI_BE 153 #define CONFIG_SYS_FSL_QSPI_BE 154 #define CONFIG_SYS_FSL_PEX_LUT_BE 155 156 #define QE_MURAM_SIZE 0x6000UL 157 #define MAX_QE_RISC 1 158 #define QE_NUM_OF_SNUM 28 159 160 #define SRDS_MAX_LANES 4 161 #define CONFIG_SYS_FSL_SRDS_1 162 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 163 164 #define CONFIG_SYS_FSL_SFP_VER_3_2 165 #define CONFIG_SYS_FSL_SEC_MON_BE 166 #define CONFIG_SYS_FSL_SEC_BE 167 #define CONFIG_SYS_FSL_SFP_BE 168 #define CONFIG_SYS_FSL_SRK_LE 169 #define CONFIG_KEY_REVOCATION 170 171 /* SMMU Defintions */ 172 #define SMMU_BASE 0x09000000 173 174 /* Generic Interrupt Controller Definitions */ 175 #define GICD_BASE 0x01401000 176 #define GICC_BASE 0x01402000 177 178 #define CONFIG_SYS_FSL_ERRATUM_A009663 179 #define CONFIG_SYS_FSL_ERRATUM_A009929 180 #else 181 #error SoC not defined 182 #endif 183 184 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 185