1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <fsl_ddrc_version.h> 11 12 #ifdef CONFIG_SYS_FSL_DDR4 13 #define CONFIG_SYS_FSL_DDRC_GEN4 14 #else 15 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ 16 #endif 17 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ 18 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 19 20 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) 21 #define CONFIG_MAX_CPUS 16 22 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 23 #ifdef CONFIG_LS2080A 24 #define CONFIG_NUM_DDR_CONTROLLERS 2 25 #endif 26 #ifdef CONFIG_LS2085A 27 #define CONFIG_NUM_DDR_CONTROLLERS 3 28 #define CONFIG_SYS_FSL_HAS_DP_DDR 29 #endif 30 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 31 #define SRDS_MAX_LANES 8 32 #define CONFIG_SYS_FSL_SRDS_1 33 #define CONFIG_SYS_FSL_SRDS_2 34 #define CONFIG_SYS_PAGE_SIZE 0x10000 35 #define CONFIG_SYS_CACHELINE_SIZE 64 36 #ifndef L1_CACHE_BYTES 37 #define L1_CACHE_SHIFT 6 38 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 39 #endif 40 41 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 42 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 43 44 /* DDR */ 45 #define CONFIG_SYS_FSL_DDR_LE 46 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 47 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 48 49 #define CONFIG_SYS_FSL_CCSR_GUR_LE 50 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 51 #define CONFIG_SYS_FSL_ESDHC_LE 52 #define CONFIG_SYS_FSL_IFC_LE 53 #define CONFIG_SYS_FSL_PEX_LUT_LE 54 55 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 56 57 /* Generic Interrupt Controller Definitions */ 58 #define GICD_BASE 0x06000000 59 #define GICR_BASE 0x06100000 60 61 /* SMMU Defintions */ 62 #define SMMU_BASE 0x05000000 /* GR0 Base */ 63 64 /* Cache Coherent Interconnect */ 65 #define CCI_MN_BASE 0x04000000 66 #define CCI_MN_RNF_NODEID_LIST 0x180 67 #define CCI_MN_DVM_DOMAIN_CTL 0x200 68 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 69 70 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 71 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 72 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 73 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 74 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 75 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 76 77 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 78 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 79 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 80 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 81 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 82 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 83 84 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 85 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 86 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 87 88 /* TZ Protection Controller Definitions */ 89 #define TZPC_BASE 0x02200000 90 #define TZPCR0SIZE_BASE (TZPC_BASE) 91 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 92 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 93 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 94 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 95 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 96 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 97 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 98 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 99 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 100 101 #define DCSR_CGACRE5 0x700070914ULL 102 #define EPU_EPCMPR5 0x700060914ULL 103 #define EPU_EPCCR5 0x700060814ULL 104 #define EPU_EPSMCR5 0x700060228ULL 105 #define EPU_EPECR5 0x700060314ULL 106 #define EPU_EPCTR5 0x700060a14ULL 107 #define EPU_EPGCR 0x700060000ULL 108 109 #define CONFIG_SYS_FSL_ERRATUM_A008336 110 #define CONFIG_SYS_FSL_ERRATUM_A008511 111 #define CONFIG_SYS_FSL_ERRATUM_A008514 112 #define CONFIG_SYS_FSL_ERRATUM_A008585 113 #define CONFIG_SYS_FSL_ERRATUM_A008751 114 #define CONFIG_SYS_FSL_ERRATUM_A009635 115 #elif defined(CONFIG_LS1043A) 116 #define CONFIG_MAX_CPUS 4 117 #define CONFIG_SYS_CACHELINE_SIZE 64 118 #define CONFIG_SYS_FMAN_V3 119 #define CONFIG_SYS_NUM_FMAN 1 120 #define CONFIG_SYS_NUM_FM1_DTSEC 7 121 #define CONFIG_SYS_NUM_FM1_10GEC 1 122 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 123 #define CONFIG_NUM_DDR_CONTROLLERS 1 124 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 125 #define CONFIG_SYS_FSL_SEC_COMPAT 5 126 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 127 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ 128 #define CONFIG_SYS_FSL_DDR_BE 129 #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 130 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE 131 132 #define CONFIG_SYS_FSL_CCSR_GUR_BE 133 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 134 #define CONFIG_SYS_FSL_IFC_BE 135 #define CONFIG_SYS_FSL_ESDHC_BE 136 #define CONFIG_SYS_FSL_WDOG_BE 137 #define CONFIG_SYS_FSL_DSPI_BE 138 #define CONFIG_SYS_FSL_QSPI_BE 139 #define CONFIG_SYS_FSL_PEX_LUT_BE 140 141 #define QE_MURAM_SIZE 0x6000UL 142 #define MAX_QE_RISC 1 143 #define QE_NUM_OF_SNUM 28 144 145 #define SRDS_MAX_LANES 4 146 #define CONFIG_SYS_FSL_SRDS_1 147 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 148 149 #define CONFIG_SYS_FSL_SFP_VER_3_2 150 #define CONFIG_SYS_FSL_SNVS_LE 151 #define CONFIG_SYS_FSL_SEC_LE 152 #define CONFIG_SYS_FSL_SFP_BE 153 #define CONFIG_SYS_FSL_SRK_LE 154 #define CONFIG_KEY_REVOCATION 155 156 /* SMMU Defintions */ 157 #define SMMU_BASE 0x09000000 158 159 /* Generic Interrupt Controller Definitions */ 160 #define GICD_BASE 0x01401000 161 #define GICC_BASE 0x01402000 162 163 #else 164 #error SoC not defined 165 #endif 166 167 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 168