1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2015, Freescale Semiconductor
4  */
5 
6 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
7 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 
9 #include <linux/kconfig.h>
10 #include <fsl_ddrc_version.h>
11 
12 #define CONFIG_STANDALONE_LOAD_ADDR	0x80300000
13 
14 /*
15  * Reserve secure memory
16  * To be aligned with MMU block size
17  */
18 #define CONFIG_SYS_MEM_RESERVE_SECURE	(66 * 1024 * 1024)	/* 66MB */
19 #define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
20 
21 #ifdef CONFIG_ARCH_LS2080A
22 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
23 #define	SRDS_MAX_LANES	8
24 #define CONFIG_SYS_PAGE_SIZE		0x10000
25 #ifndef L1_CACHE_BYTES
26 #define L1_CACHE_SHIFT		6
27 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
28 #define CONFIG_FSL_TZASC_400
29 #endif
30 
31 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
34 
35 /* DDR */
36 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
37 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
38 
39 #define CONFIG_SYS_FSL_CCSR_GUR_LE
40 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
41 #define CONFIG_SYS_FSL_ESDHC_LE
42 #define CONFIG_SYS_FSL_IFC_LE
43 #define CONFIG_SYS_FSL_PEX_LUT_LE
44 
45 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
46 
47 /* Generic Interrupt Controller Definitions */
48 #define GICD_BASE			0x06000000
49 #define GICR_BASE			0x06100000
50 
51 /* SMMU Defintions */
52 #define SMMU_BASE			0x05000000 /* GR0 Base */
53 
54 /* SFP */
55 #define CONFIG_SYS_FSL_SFP_VER_3_4
56 #define CONFIG_SYS_FSL_SFP_LE
57 #define CONFIG_SYS_FSL_SRK_LE
58 
59 /* Security Monitor */
60 #define CONFIG_SYS_FSL_SEC_MON_LE
61 
62 /* Secure Boot */
63 #define CONFIG_ESBC_HDR_LS
64 
65 /* DCFG - GUR */
66 #define CONFIG_SYS_FSL_CCSR_GUR_LE
67 
68 /* Cache Coherent Interconnect */
69 #define CCI_MN_BASE			0x04000000
70 #define CCI_MN_RNF_NODEID_LIST		0x180
71 #define CCI_MN_DVM_DOMAIN_CTL		0x200
72 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
73 
74 #define CCI_HN_F_0_BASE			(CCI_MN_BASE + 0x200000)
75 #define CCI_HN_F_1_BASE			(CCI_MN_BASE + 0x210000)
76 #define CCN_HN_F_SAM_CTL		0x8	/* offset on base HN_F base */
77 #define CCN_HN_F_SAM_NODEID_MASK	0x7f
78 #define CCN_HN_F_SAM_NODEID_DDR0	0x4
79 #define CCN_HN_F_SAM_NODEID_DDR1	0xe
80 
81 #define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
82 #define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
83 #define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
84 #define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
85 #define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
86 #define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
87 
88 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
89 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
90 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
91 
92 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
93 
94 /* TZ Protection Controller Definitions */
95 #define TZPC_BASE				0x02200000
96 #define TZPCR0SIZE_BASE				(TZPC_BASE)
97 #define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
98 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
99 #define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
100 #define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
101 #define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
102 #define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
103 #define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
104 #define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
105 #define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
106 
107 #define DCSR_CGACRE5		0x700070914ULL
108 #define EPU_EPCMPR5		0x700060914ULL
109 #define EPU_EPCCR5		0x700060814ULL
110 #define EPU_EPSMCR5		0x700060228ULL
111 #define EPU_EPECR5		0x700060314ULL
112 #define EPU_EPCTR5		0x700060a14ULL
113 #define EPU_EPGCR		0x700060000ULL
114 
115 #define CONFIG_SYS_FSL_ERRATUM_A008751
116 
117 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
118 
119 #elif defined(CONFIG_ARCH_LS1088A)
120 #define CONFIG_SYS_FSL_NUM_CC_PLLS		3
121 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
122 #define CONFIG_GICV3
123 #define CONFIG_FSL_TZPC_BP147
124 #define CONFIG_FSL_TZASC_400
125 #define CONFIG_SYS_PAGE_SIZE		0x10000
126 
127 #define	SRDS_MAX_LANES	4
128 
129 /* TZ Protection Controller Definitions */
130 #define TZPC_BASE				0x02200000
131 #define TZPCR0SIZE_BASE				(TZPC_BASE)
132 #define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
133 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
134 #define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
135 #define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
136 #define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
137 #define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
138 #define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
139 #define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
140 #define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
141 
142 /* Generic Interrupt Controller Definitions */
143 #define GICD_BASE			0x06000000
144 #define GICR_BASE			0x06100000
145 
146 /* SMMU Defintions */
147 #define SMMU_BASE			0x05000000 /* GR0 Base */
148 
149 /* DDR */
150 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
151 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
152 
153 #define CONFIG_SYS_FSL_CCSR_GUR_LE
154 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
155 #define CONFIG_SYS_FSL_ESDHC_LE
156 #define CONFIG_SYS_FSL_IFC_LE
157 #define CONFIG_SYS_FSL_PEX_LUT_LE
158 
159 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
160 
161 /* SFP */
162 #define CONFIG_SYS_FSL_SFP_VER_3_4
163 #define CONFIG_SYS_FSL_SFP_LE
164 #define CONFIG_SYS_FSL_SRK_LE
165 
166 /* Security Monitor */
167 #define CONFIG_SYS_FSL_SEC_MON_LE
168 
169 /* Secure Boot */
170 #define CONFIG_ESBC_HDR_LS
171 
172 /* DCFG - GUR */
173 #define CONFIG_SYS_FSL_CCSR_GUR_LE
174 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
175 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
176 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
177 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
178 
179 #elif defined(CONFIG_FSL_LSCH2)
180 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
181 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
182 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
183 
184 #define DCSR_DCFG_SBEESR2			0x20140534
185 #define DCSR_DCFG_MBEESR2			0x20140544
186 
187 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
188 #define CONFIG_SYS_FSL_ESDHC_BE
189 #define CONFIG_SYS_FSL_WDOG_BE
190 #define CONFIG_SYS_FSL_DSPI_BE
191 #define CONFIG_SYS_FSL_QSPI_BE
192 #define CONFIG_SYS_FSL_CCSR_GUR_BE
193 #define CONFIG_SYS_FSL_PEX_LUT_BE
194 
195 /* SoC related */
196 #ifdef CONFIG_ARCH_LS1043A
197 #define CONFIG_SYS_FMAN_V3
198 #define CONFIG_SYS_FSL_QMAN_V3
199 #define CONFIG_SYS_NUM_FMAN			1
200 #define CONFIG_SYS_NUM_FM1_DTSEC		7
201 #define CONFIG_SYS_NUM_FM1_10GEC		1
202 #define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
203 #define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
204 
205 #define QE_MURAM_SIZE		0x6000UL
206 #define MAX_QE_RISC		1
207 #define QE_NUM_OF_SNUM		28
208 
209 #define CONFIG_SYS_FSL_IFC_BE
210 #define CONFIG_SYS_FSL_SFP_VER_3_2
211 #define CONFIG_SYS_FSL_SEC_MON_BE
212 #define CONFIG_SYS_FSL_SFP_BE
213 #define CONFIG_SYS_FSL_SRK_LE
214 #define CONFIG_KEY_REVOCATION
215 
216 /* SMMU Defintions */
217 #define SMMU_BASE		0x09000000
218 
219 /* Generic Interrupt Controller Definitions */
220 #define GICD_BASE		0x01401000
221 #define GICC_BASE		0x01402000
222 #define GICH_BASE		0x01404000
223 #define GICV_BASE		0x01406000
224 #define GICD_SIZE		0x1000
225 #define GICC_SIZE		0x2000
226 #define GICH_SIZE		0x2000
227 #define GICV_SIZE		0x2000
228 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
229 #define GICD_BASE_64K		0x01410000
230 #define GICC_BASE_64K		0x01420000
231 #define GICH_BASE_64K		0x01440000
232 #define GICV_BASE_64K		0x01460000
233 #define GICD_SIZE_64K		0x10000
234 #define GICC_SIZE_64K		0x20000
235 #define GICH_SIZE_64K		0x20000
236 #define GICV_SIZE_64K		0x20000
237 #endif
238 
239 #define DCFG_CCSR_SVR		0x1ee00a4
240 #define REV1_0			0x10
241 #define REV1_1			0x11
242 #define GIC_ADDR_BIT		31
243 #define SCFG_GIC400_ALIGN	0x1570188
244 
245 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
246 
247 #elif defined(CONFIG_ARCH_LS1012A)
248 #define GICD_BASE		0x01401000
249 #define GICC_BASE		0x01402000
250 #define CONFIG_SYS_FSL_SFP_VER_3_2
251 #define CONFIG_SYS_FSL_SEC_MON_BE
252 #define CONFIG_SYS_FSL_SFP_BE
253 #define CONFIG_SYS_FSL_SRK_LE
254 #define CONFIG_KEY_REVOCATION
255 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
256 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
257 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
258 
259 #elif defined(CONFIG_ARCH_LS1046A)
260 #define CONFIG_SYS_FMAN_V3
261 #define CONFIG_SYS_FSL_QMAN_V3
262 #define CONFIG_SYS_NUM_FMAN			1
263 #define CONFIG_SYS_NUM_FM1_DTSEC		8
264 #define CONFIG_SYS_NUM_FM1_10GEC		2
265 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
266 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
267 
268 #define CONFIG_SYS_FSL_IFC_BE
269 #define CONFIG_SYS_FSL_SFP_VER_3_2
270 #define CONFIG_SYS_FSL_SEC_MON_BE
271 #define CONFIG_SYS_FSL_SFP_BE
272 #define CONFIG_SYS_FSL_SRK_LE
273 #define CONFIG_KEY_REVOCATION
274 
275 /* SMMU Defintions */
276 #define SMMU_BASE		0x09000000
277 
278 /* Generic Interrupt Controller Definitions */
279 #define GICD_BASE		0x01410000
280 #define GICC_BASE		0x01420000
281 
282 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
283 #else
284 #error SoC not defined
285 #endif
286 #endif
287 
288 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
289