1 /* 2 * Copyright 2015, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10 #include <fsl_ddrc_version.h> 11 12 #ifdef CONFIG_SYS_FSL_DDR4 13 #define CONFIG_SYS_FSL_DDRC_GEN4 14 #else 15 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ 16 #endif 17 18 #ifndef CONFIG_LS1012A 19 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ 20 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 21 #endif 22 23 /* 24 * Reserve secure memory 25 * To be aligned with MMU block size 26 */ 27 #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ 28 29 #ifdef CONFIG_LS2080A 30 #define CONFIG_MAX_CPUS 16 31 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 32 #define CONFIG_NUM_DDR_CONTROLLERS 3 33 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ 34 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 35 #define SRDS_MAX_LANES 8 36 #define CONFIG_SYS_FSL_SRDS_1 37 #define CONFIG_SYS_FSL_SRDS_2 38 #define CONFIG_SYS_PAGE_SIZE 0x10000 39 #ifndef L1_CACHE_BYTES 40 #define L1_CACHE_SHIFT 6 41 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 42 #endif 43 44 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 45 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 46 47 /* DDR */ 48 #define CONFIG_SYS_FSL_DDR_LE 49 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 50 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 51 52 #define CONFIG_SYS_FSL_CCSR_GUR_LE 53 #define CONFIG_SYS_FSL_CCSR_SCFG_LE 54 #define CONFIG_SYS_FSL_ESDHC_LE 55 #define CONFIG_SYS_FSL_IFC_LE 56 #define CONFIG_SYS_FSL_PEX_LUT_LE 57 58 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN 59 60 /* Generic Interrupt Controller Definitions */ 61 #define GICD_BASE 0x06000000 62 #define GICR_BASE 0x06100000 63 64 /* SMMU Defintions */ 65 #define SMMU_BASE 0x05000000 /* GR0 Base */ 66 67 /* SFP */ 68 #define CONFIG_SYS_FSL_SFP_VER_3_4 69 #define CONFIG_SYS_FSL_SFP_LE 70 #define CONFIG_SYS_FSL_SRK_LE 71 72 /* SEC */ 73 #define CONFIG_SYS_FSL_SEC_LE 74 #define CONFIG_SYS_FSL_SEC_COMPAT 5 75 76 /* Security Monitor */ 77 #define CONFIG_SYS_FSL_SEC_MON_LE 78 79 /* Secure Boot */ 80 #define CONFIG_ESBC_HDR_LS 81 82 /* DCFG - GUR */ 83 #define CONFIG_SYS_FSL_CCSR_GUR_LE 84 85 /* Cache Coherent Interconnect */ 86 #define CCI_MN_BASE 0x04000000 87 #define CCI_MN_RNF_NODEID_LIST 0x180 88 #define CCI_MN_DVM_DOMAIN_CTL 0x200 89 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 90 91 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 92 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 93 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 94 #define CCN_HN_F_SAM_NODEID_MASK 0x7f 95 #define CCN_HN_F_SAM_NODEID_DDR0 0x4 96 #define CCN_HN_F_SAM_NODEID_DDR1 0xe 97 98 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 99 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 100 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 101 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 102 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 103 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 104 105 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 106 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 107 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 108 109 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 110 111 /* TZ Protection Controller Definitions */ 112 #define TZPC_BASE 0x02200000 113 #define TZPCR0SIZE_BASE (TZPC_BASE) 114 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 115 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 116 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 117 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 118 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 119 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 120 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 121 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 122 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 123 124 #define DCSR_CGACRE5 0x700070914ULL 125 #define EPU_EPCMPR5 0x700060914ULL 126 #define EPU_EPCCR5 0x700060814ULL 127 #define EPU_EPSMCR5 0x700060228ULL 128 #define EPU_EPECR5 0x700060314ULL 129 #define EPU_EPCTR5 0x700060a14ULL 130 #define EPU_EPGCR 0x700060000ULL 131 132 #define CONFIG_SYS_FSL_ERRATUM_A008336 133 #define CONFIG_SYS_FSL_ERRATUM_A008511 134 #define CONFIG_SYS_FSL_ERRATUM_A008514 135 #define CONFIG_SYS_FSL_ERRATUM_A008585 136 #define CONFIG_SYS_FSL_ERRATUM_A008751 137 #define CONFIG_SYS_FSL_ERRATUM_A009635 138 #define CONFIG_SYS_FSL_ERRATUM_A009663 139 #define CONFIG_SYS_FSL_ERRATUM_A009801 140 #define CONFIG_SYS_FSL_ERRATUM_A009803 141 #define CONFIG_SYS_FSL_ERRATUM_A009942 142 #define CONFIG_SYS_FSL_ERRATUM_A010165 143 144 /* ARM A57 CORE ERRATA */ 145 #define CONFIG_ARM_ERRATA_826974 146 #define CONFIG_ARM_ERRATA_828024 147 #define CONFIG_ARM_ERRATA_829520 148 #define CONFIG_ARM_ERRATA_833471 149 150 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 151 #elif defined(CONFIG_FSL_LSCH2) 152 #define CONFIG_NUM_DDR_CONTROLLERS 1 153 #define CONFIG_SYS_FSL_SEC_COMPAT 5 154 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 155 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ 156 #define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 157 158 #define CONFIG_SYS_FSL_CCSR_SCFG_BE 159 #define CONFIG_SYS_FSL_ESDHC_BE 160 #define CONFIG_SYS_FSL_WDOG_BE 161 #define CONFIG_SYS_FSL_DSPI_BE 162 #define CONFIG_SYS_FSL_QSPI_BE 163 #define CONFIG_SYS_FSL_CCSR_GUR_BE 164 #define CONFIG_SYS_FSL_PEX_LUT_BE 165 #define CONFIG_SYS_FSL_SEC_BE 166 167 #define CONFIG_SYS_FSL_SRDS_1 168 /* SoC related */ 169 #ifdef CONFIG_LS1043A 170 #define CONFIG_MAX_CPUS 4 171 #define CONFIG_SYS_FMAN_V3 172 #define CONFIG_SYS_NUM_FMAN 1 173 #define CONFIG_SYS_NUM_FM1_DTSEC 7 174 #define CONFIG_SYS_NUM_FM1_10GEC 1 175 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 176 #define CONFIG_SYS_FSL_DDR_BE 177 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 178 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 179 180 #define QE_MURAM_SIZE 0x6000UL 181 #define MAX_QE_RISC 1 182 #define QE_NUM_OF_SNUM 28 183 184 #define CONFIG_SYS_FSL_IFC_BE 185 #define CONFIG_SYS_FSL_SFP_VER_3_2 186 #define CONFIG_SYS_FSL_SEC_MON_BE 187 #define CONFIG_SYS_FSL_SFP_BE 188 #define CONFIG_SYS_FSL_SRK_LE 189 #define CONFIG_KEY_REVOCATION 190 191 /* SMMU Defintions */ 192 #define SMMU_BASE 0x09000000 193 194 /* Generic Interrupt Controller Definitions */ 195 #define GICD_BASE 0x01401000 196 #define GICC_BASE 0x01402000 197 198 #define CONFIG_SYS_FSL_ERRATUM_A008850 199 #define CONFIG_SYS_FSL_ERRATUM_A009663 200 #define CONFIG_SYS_FSL_ERRATUM_A009929 201 #define CONFIG_SYS_FSL_ERRATUM_A009942 202 #define CONFIG_SYS_FSL_ERRATUM_A009660 203 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 204 #elif defined(CONFIG_LS1012A) 205 #define CONFIG_MAX_CPUS 1 206 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 207 208 #define GICD_BASE 0x01401000 209 #define GICC_BASE 0x01402000 210 #elif defined(CONFIG_LS1046A) 211 #define CONFIG_MAX_CPUS 4 212 #define CONFIG_SYS_FMAN_V3 213 #define CONFIG_SYS_NUM_FMAN 1 214 #define CONFIG_SYS_NUM_FM1_DTSEC 8 215 #define CONFIG_SYS_NUM_FM1_10GEC 2 216 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 217 #define CONFIG_SYS_FSL_DDR_BE 218 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 219 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE 220 221 #define CONFIG_SYS_FSL_SRDS_2 222 #define CONFIG_SYS_FSL_IFC_BE 223 #define CONFIG_SYS_FSL_SFP_VER_3_2 224 #define CONFIG_SYS_FSL_SNVS_LE 225 #define CONFIG_SYS_FSL_SFP_BE 226 #define CONFIG_SYS_FSL_SRK_LE 227 #define CONFIG_KEY_REVOCATION 228 229 /* SMMU Defintions */ 230 #define SMMU_BASE 0x09000000 231 232 /* Generic Interrupt Controller Definitions */ 233 #define GICD_BASE 0x01410000 234 #define GICC_BASE 0x01420000 235 236 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 237 #else 238 #error SoC not defined 239 #endif 240 #endif 241 242 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 243