1 /*
2  * Copyright 2015, Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
9 
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
12 
13 #define CONFIG_STANDALONE_LOAD_ADDR	0x80300000
14 
15 /*
16  * Reserve secure memory
17  * To be aligned with MMU block size
18  */
19 #define CONFIG_SYS_MEM_RESERVE_SECURE	(2048 * 1024)	/* 2MB */
20 #define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
21 
22 #ifdef CONFIG_ARCH_LS2080A
23 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
24 #define	SRDS_MAX_LANES	8
25 #define CONFIG_SYS_PAGE_SIZE		0x10000
26 #ifndef L1_CACHE_BYTES
27 #define L1_CACHE_SHIFT		6
28 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
29 #define CONFIG_FSL_TZASC_400
30 #endif
31 
32 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
33 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
34 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
35 
36 /* DDR */
37 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
38 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
39 
40 #define CONFIG_SYS_FSL_CCSR_GUR_LE
41 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
42 #define CONFIG_SYS_FSL_ESDHC_LE
43 #define CONFIG_SYS_FSL_IFC_LE
44 #define CONFIG_SYS_FSL_PEX_LUT_LE
45 
46 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
47 
48 /* Generic Interrupt Controller Definitions */
49 #define GICD_BASE			0x06000000
50 #define GICR_BASE			0x06100000
51 
52 /* SMMU Defintions */
53 #define SMMU_BASE			0x05000000 /* GR0 Base */
54 
55 /* SFP */
56 #define CONFIG_SYS_FSL_SFP_VER_3_4
57 #define CONFIG_SYS_FSL_SFP_LE
58 #define CONFIG_SYS_FSL_SRK_LE
59 
60 /* Security Monitor */
61 #define CONFIG_SYS_FSL_SEC_MON_LE
62 
63 /* Secure Boot */
64 #define CONFIG_ESBC_HDR_LS
65 
66 /* DCFG - GUR */
67 #define CONFIG_SYS_FSL_CCSR_GUR_LE
68 
69 /* Cache Coherent Interconnect */
70 #define CCI_MN_BASE			0x04000000
71 #define CCI_MN_RNF_NODEID_LIST		0x180
72 #define CCI_MN_DVM_DOMAIN_CTL		0x200
73 #define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
74 
75 #define CCI_HN_F_0_BASE			(CCI_MN_BASE + 0x200000)
76 #define CCI_HN_F_1_BASE			(CCI_MN_BASE + 0x210000)
77 #define CCN_HN_F_SAM_CTL		0x8	/* offset on base HN_F base */
78 #define CCN_HN_F_SAM_NODEID_MASK	0x7f
79 #define CCN_HN_F_SAM_NODEID_DDR0	0x4
80 #define CCN_HN_F_SAM_NODEID_DDR1	0xe
81 
82 #define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
83 #define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
84 #define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
85 #define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
86 #define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
87 #define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
88 
89 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
90 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
91 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
92 
93 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
94 
95 /* TZ Protection Controller Definitions */
96 #define TZPC_BASE				0x02200000
97 #define TZPCR0SIZE_BASE				(TZPC_BASE)
98 #define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
99 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
100 #define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
101 #define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
102 #define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
103 #define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
104 #define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
105 #define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
106 #define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
107 
108 #define DCSR_CGACRE5		0x700070914ULL
109 #define EPU_EPCMPR5		0x700060914ULL
110 #define EPU_EPCCR5		0x700060814ULL
111 #define EPU_EPSMCR5		0x700060228ULL
112 #define EPU_EPECR5		0x700060314ULL
113 #define EPU_EPCTR5		0x700060a14ULL
114 #define EPU_EPGCR		0x700060000ULL
115 
116 #define CONFIG_SYS_FSL_ERRATUM_A008751
117 
118 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
119 
120 #elif defined(CONFIG_ARCH_LS1088A)
121 #define CONFIG_SYS_FSL_NUM_CC_PLLS		3
122 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
123 #define CONFIG_GICV3
124 #define CONFIG_FSL_TZPC_BP147
125 #define CONFIG_FSL_TZASC_400
126 #define CONFIG_SYS_PAGE_SIZE		0x10000
127 
128 #define	SRDS_MAX_LANES	4
129 
130 /* TZ Protection Controller Definitions */
131 #define TZPC_BASE				0x02200000
132 #define TZPCR0SIZE_BASE				(TZPC_BASE)
133 #define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
134 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
135 #define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
136 #define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
137 #define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
138 #define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
139 #define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
140 #define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
141 #define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
142 
143 /* Generic Interrupt Controller Definitions */
144 #define GICD_BASE			0x06000000
145 #define GICR_BASE			0x06100000
146 
147 /* SMMU Defintions */
148 #define SMMU_BASE			0x05000000 /* GR0 Base */
149 
150 /* DDR */
151 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
152 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
153 
154 #define CONFIG_SYS_FSL_CCSR_GUR_LE
155 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
156 #define CONFIG_SYS_FSL_ESDHC_LE
157 #define CONFIG_SYS_FSL_IFC_LE
158 #define CONFIG_SYS_FSL_PEX_LUT_LE
159 
160 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
161 
162 /* SFP */
163 #define CONFIG_SYS_FSL_SFP_VER_3_4
164 #define CONFIG_SYS_FSL_SFP_LE
165 #define CONFIG_SYS_FSL_SRK_LE
166 
167 /* Security Monitor */
168 #define CONFIG_SYS_FSL_SEC_MON_LE
169 
170 /* Secure Boot */
171 #define CONFIG_ESBC_HDR_LS
172 
173 /* DCFG - GUR */
174 #define CONFIG_SYS_FSL_CCSR_GUR_LE
175 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
176 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
177 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
178 #define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
179 
180 #elif defined(CONFIG_FSL_LSCH2)
181 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
182 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
183 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
184 
185 #define DCSR_DCFG_SBEESR2			0x20140534
186 #define DCSR_DCFG_MBEESR2			0x20140544
187 
188 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
189 #define CONFIG_SYS_FSL_ESDHC_BE
190 #define CONFIG_SYS_FSL_WDOG_BE
191 #define CONFIG_SYS_FSL_DSPI_BE
192 #define CONFIG_SYS_FSL_QSPI_BE
193 #define CONFIG_SYS_FSL_CCSR_GUR_BE
194 #define CONFIG_SYS_FSL_PEX_LUT_BE
195 
196 /* SoC related */
197 #ifdef CONFIG_ARCH_LS1043A
198 #define CONFIG_SYS_FMAN_V3
199 #define CONFIG_SYS_NUM_FMAN			1
200 #define CONFIG_SYS_NUM_FM1_DTSEC		7
201 #define CONFIG_SYS_NUM_FM1_10GEC		1
202 #define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
203 #define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
204 
205 #define QE_MURAM_SIZE		0x6000UL
206 #define MAX_QE_RISC		1
207 #define QE_NUM_OF_SNUM		28
208 
209 #define CONFIG_SYS_FSL_IFC_BE
210 #define CONFIG_SYS_FSL_SFP_VER_3_2
211 #define CONFIG_SYS_FSL_SEC_MON_BE
212 #define CONFIG_SYS_FSL_SFP_BE
213 #define CONFIG_SYS_FSL_SRK_LE
214 #define CONFIG_KEY_REVOCATION
215 
216 /* SMMU Defintions */
217 #define SMMU_BASE		0x09000000
218 
219 /* Generic Interrupt Controller Definitions */
220 #define GICD_BASE		0x01401000
221 #define GICC_BASE		0x01402000
222 #define GICH_BASE		0x01404000
223 #define GICV_BASE		0x01406000
224 #define GICD_SIZE		0x1000
225 #define GICC_SIZE		0x2000
226 #define GICH_SIZE		0x2000
227 #define GICV_SIZE		0x2000
228 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
229 #define GICD_BASE_64K		0x01410000
230 #define GICC_BASE_64K		0x01420000
231 #define GICH_BASE_64K		0x01440000
232 #define GICV_BASE_64K		0x01460000
233 #define GICD_SIZE_64K		0x10000
234 #define GICC_SIZE_64K		0x20000
235 #define GICH_SIZE_64K		0x20000
236 #define GICV_SIZE_64K		0x20000
237 #endif
238 
239 #define DCFG_CCSR_SVR		0x1ee00a4
240 #define REV1_0			0x10
241 #define REV1_1			0x11
242 #define GIC_ADDR_BIT		31
243 #define SCFG_GIC400_ALIGN	0x1570188
244 
245 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
246 
247 #elif defined(CONFIG_ARCH_LS1012A)
248 #define GICD_BASE		0x01401000
249 #define GICC_BASE		0x01402000
250 #define CONFIG_SYS_FSL_SFP_VER_3_2
251 #define CONFIG_SYS_FSL_SEC_MON_BE
252 #define CONFIG_SYS_FSL_SFP_BE
253 #define CONFIG_SYS_FSL_SRK_LE
254 #define CONFIG_KEY_REVOCATION
255 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
256 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
257 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
258 
259 #elif defined(CONFIG_ARCH_LS1046A)
260 #define CONFIG_SYS_FMAN_V3
261 #define CONFIG_SYS_NUM_FMAN			1
262 #define CONFIG_SYS_NUM_FM1_DTSEC		8
263 #define CONFIG_SYS_NUM_FM1_10GEC		2
264 #define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
265 #define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
266 
267 #define CONFIG_SYS_FSL_IFC_BE
268 #define CONFIG_SYS_FSL_SFP_VER_3_2
269 #define CONFIG_SYS_FSL_SEC_MON_BE
270 #define CONFIG_SYS_FSL_SFP_BE
271 #define CONFIG_SYS_FSL_SRK_LE
272 #define CONFIG_KEY_REVOCATION
273 
274 /* SMMU Defintions */
275 #define SMMU_BASE		0x09000000
276 
277 /* Generic Interrupt Controller Definitions */
278 #define GICD_BASE		0x01410000
279 #define GICC_BASE		0x01420000
280 
281 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
282 #else
283 #error SoC not defined
284 #endif
285 #endif
286 
287 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
288