1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #ifndef _ASM_ARCH_SCU_AST2600_H 7 #define _ASM_ARCH_SCU_AST2600_H 8 9 #define AST2600_CLK_IN 25000000 10 11 struct ast2600_clk_priv { 12 struct ast2600_scu *scu; 13 }; 14 15 struct hw_strap { 16 u32 hwstrap; /* 0x508 */ 17 u32 hwstrap_clr; /* 0x504 */ 18 u32 hwstrap_protect; /* 0x508 */ 19 }; 20 21 struct ast2600_scu { 22 u32 protection_key; /* 0x000 */ 23 u32 chip_id0; /* 0x004 */ 24 u32 reserve_0x08; /* 0x008 */ 25 u32 reserve_0x0C; /* 0x00C */ 26 u32 reserve_0x10; /* 0x010 */ 27 u32 chip_id1; /* 0x014 */ 28 u32 reserve_0x18; /* 0x018 */ 29 u32 reserve_0x1C; /* 0x01C */ 30 u32 reserve_0x20; /* 0x020 */ 31 u32 reserve_0x24; /* 0x024 */ 32 u32 reserve_0x28; /* 0x028 */ 33 u32 reserve_0x2c; /* 0x02C */ 34 u32 reserve_0x30; /* 0x030 */ 35 u32 reserve_0x34; /* 0x034 */ 36 u32 reserve_0x38; /* 0x038 */ 37 u32 reserve_0x3C; /* 0x03C */ 38 u32 sysreset_ctrl1; /* 0x040 */ 39 u32 sysreset_clr_ctrl1; /* 0x044 */ 40 u32 reserve_0x48; /* 0x048 */ 41 u32 reserve_0x4C; /* 0x04C */ 42 u32 sysreset_ctrl2; /* 0x050 */ 43 u32 sysreset_clr_ctrl2; /* 0x054 */ 44 u32 reserve_0x58; /* 0x058 */ 45 u32 reserve_0x5C; /* 0x05C */ 46 u32 extrst_sel1; /* 0x060 */ 47 u32 sysrst_evet_log1_1; /* 0x064 */ 48 u32 sysrst_evet_log1_2; /* 0x068 */ 49 u32 reserve_0x6C; /* 0x06C */ 50 u32 extrst_sel2; /* 0x070 */ 51 u32 sysrst_evet_log2_1; /* 0x074 */ 52 u32 sysrst_evet_log2_2; /* 0x078 */ 53 u32 reserve_0x7C; /* 0x07C */ 54 u32 clk_stop_ctrl1; /* 0x080 */ 55 u32 clk_stop_clr_ctrl1; /* 0x084 */ 56 u32 reserve_0x88; /* 0x088 */ 57 u32 reserve_0x8C; /* 0x08C */ 58 u32 clk_stop_ctrl2; /* 0x090 */ 59 u32 clk_stop_clr_ctrl2; /* 0x094 */ 60 u32 reserve_0x98; /* 0x098 */ 61 u32 reserve_0x9C; /* 0x09C */ 62 u32 reserve_0xA0; /* 0x0A0 */ 63 u32 reserve_0xA4; /* 0x0A4 */ 64 u32 reserve_0xA8; /* 0x0A8 */ 65 u32 reserve_0xAC; /* 0x0AC */ 66 u32 reserve_0xB0; /* 0x0B0 */ 67 u32 reserve_0xB4; /* 0x0B4 */ 68 u32 reserve_0xB8; /* 0x0B8 */ 69 u32 reserve_0xBC; /* 0x0BC */ 70 u32 misc_ctrl1; /* 0x0C0 */ 71 u32 misc_ctrl2; /* 0x0C4 */ 72 u32 backdoor_ctrl; /* 0x0C8 */ 73 u32 reserve_0xCC; /* 0x0CC */ 74 u32 misc_ctrl3; /* 0x0D0 */ 75 u32 misc_ctrl4; /* 0x0D4 */ 76 u32 reserve_0xD8; /* 0x0D8 */ 77 u32 reserve_0xDC; /* 0x0DC */ 78 u32 reserve_0xE0; /* 0x0E0 */ 79 u32 reserve_0xE4; /* 0x0E4 */ 80 u32 reserve_0xE8; /* 0x0E8 */ 81 u32 reserve_0xEC; /* 0x0EC */ 82 u32 reserve_0xF0; /* 0x0F0 */ 83 u32 reserve_0xF4; /* 0x0F4 */ 84 u32 reserve_0xF8; /* 0x0F8 */ 85 u32 reserve_0xFC; /* 0x0FC */ 86 u32 soc_scratch[4]; /* 0x100 */ 87 u32 reserve_0x110; /* 0x110 */ 88 u32 reserve_0x114; /* 0x114 */ 89 u32 reserve_0x118; /* 0x118 */ 90 u32 reserve_0x11C; /* 0x11C */ 91 u32 cpu_scratch_wp; /* 0x120 */ 92 u32 reserve_0x124[23]; /* 0x124 */ 93 u32 cpu_scratch[32]; /* 0x180 */ 94 u32 h_pll_param; /* 0x200 */ 95 u32 h_pll_ext_param; /* 0x204 */ 96 u32 reserve_0x208; /* 0x208 */ 97 u32 reserve_0x20C; /* 0x20C */ 98 u32 a_pll_param; /* 0x210 */ 99 u32 a_pll_ext_param; /* 0x214 */ 100 u32 reserve_0x218; /* 0x218 */ 101 u32 reserve_0x21C; /* 0x21C */ 102 u32 m_pll_param; /* 0x220 */ 103 u32 m_pll_ext_param; /* 0x224 */ 104 u32 reserve_0x228; /* 0x228 */ 105 u32 reserve_0x22C; /* 0x22C */ 106 u32 reserve_0x230[4]; /* 0x230 */ 107 u32 e_pll_param; /* 0x240 */ 108 u32 e_pll_ext_param; /* 0x244 */ 109 u32 reserve_0x248; /* 0x248 */ 110 u32 reserve_0x24C; /* 0x24C */ 111 u32 reserve_0x250[4]; /* 0x250 */ 112 u32 d_pll_param; /* 0x260 */ 113 u32 d_pll_ext_param; /* 0x264 */ 114 u32 reserve_0x268; /* 0x268 */ 115 u32 reserve_0x26C; /* 0x26C */ 116 u32 reserve_0x270[36]; /* 0x270 */ 117 u32 clk_sel1; /* 0x300 */ 118 u32 clk_sel2; /* 0x304 */ 119 u32 clk_sel3; /* 0x308 */ 120 u32 reserve_0x30C; /* 0x30C */ 121 u32 clk_sel4; /* 0x310 */ 122 u32 clk_sel5; /* 0x314 */ 123 u32 reserve_0x318; /* 0x318 */ 124 u32 reserve_0x31C; /* 0x31C */ 125 u32 freq_counter_ctrl1; /* 0x320 */ 126 u32 freq_counter_cmp1; /* 0x324 */ 127 u32 reserve_0x328; /* 0x328 */ 128 u32 uart_24m_ref_hpll; /* 0x32C */ 129 u32 freq_counter_ctrl2; /* 0x330 */ 130 u32 freq_counter_cmp2; /* 0x334 */ 131 u32 uart_24m_ref_uxclk; /* 0x338 */ 132 u32 uart_24m_ref_huxclk; /* 0x33C */ 133 u32 mac12_clk_delay; /* 0x340 */ 134 u32 reserve_0x344; /* 0x344 */ 135 u32 mac12_clk_delay_100M;/* 0x348 */ 136 u32 mac12_clk_delay_10M;/* 0x34c */ 137 u32 mac34_clk_delay; /* 0x350 */ 138 u32 reserve_0x354; /* 0x354 */ 139 u32 mac34_clk_delay_100M;/* 0x358 */ 140 u32 mac34_clk_delay_10M;/* 0x35c */ 141 u32 clk_duty_meas_ctrl; /* 0x360 */ 142 u32 clk_duty_sel0; /* 0x364 */ 143 u32 clk_duty_sel1; /* 0x368 */ 144 u32 clk_duty_meas_res; /* 0x36C */ 145 u32 clk_duty_meas_ctr2; /* 0x370 */ 146 u32 clk_duty_sel2; /* 0x374 */ 147 u32 reserve_0x378[34]; /* 0x378 */ 148 u32 pinmux_ctrl1[64]; /* 0x400 ~ 0x500 */ 149 struct hw_strap hwstrap1; /* 0x500 */ 150 u32 reserve_0x50C; /* 0x50C */ 151 struct hw_strap hwstrap2; /* 0x510 */ 152 u32 reserve_0x51C; /* 0x51C */ 153 u32 rng_ctrl; /* 0x520 */ 154 u32 rng_data; /* 0x524 */ 155 u32 reserve_0x528[6]; /* 0x528 */ 156 u32 pwr_save_wakeup_en1;/* 0x540 */ 157 u32 pwr_save_wakeup_ctrl1;/* 0x544 */ 158 u32 reserve_0x548[2]; /* 0x548 */ 159 u32 pwr_save_wakeup_en2;/* 0x550 */ 160 u32 pwr_save_wakeup_ctrl2;/* 0x554 */ 161 u32 reserve_0x558[2]; /* 0x558 */ 162 u32 intr1_ctrl_sts; /* 0x560 */ 163 u32 reserve_0x564[3]; /* 0x564 */ 164 u32 intr2_ctrl_sts; /* 0x570 */ 165 u32 reserve_0x574[3]; /* 0x574 */ 166 u32 reserve_0x580[4]; /* 0x580 */ 167 u32 opt_ctrl; /* 0x590 */ 168 u32 hw_config; /* 0x594 */ 169 u32 reserve_0x598[6]; /* 0x598 */ 170 u32 chip_unique_id[8]; /* 0x5B0 */ 171 u32 reserve_0x5E0[8]; /* 0x5E0 */ 172 u32 disgpio_in_pull_down0; /* 0x610 */ 173 u32 disgpio_in_pull_down1; /* 0x614 */ 174 u32 disgpio_in_pull_down2; /* 0x618 */ 175 u32 disgpio_in_pull_down3; /* 0x61C */ 176 u32 reserve_0x620[4]; /* 0x620 */ 177 u32 disgpio_in_pull_down4; /* 0x630 */ 178 u32 disgpio_in_pull_down5; /* 0x634 */ 179 u32 disgpio_in_pull_down6; /* 0x638 */ 180 u32 reserve_0x63C[5]; /* 0x63Cs */ 181 u32 sli_driving_strength; /* 0x650 */ 182 u32 reserve_0x654[235]; /* 0x654 */ 183 u32 cm3_ctrl; /* 0xA00 */ 184 u32 cm3_base; /* 0xA04 */ 185 u32 cm3_instr_mem_addr; /* 0xA08 */ 186 u32 cm3_data_mem_addr; /* 0xA0C */ 187 u32 reserve_0xA10[12]; /* 0xA10 */ 188 u32 cm3_cache_area; /* 0xA40 */ 189 u32 cm3_cache_invalid_ctrl; /* 0xA44 */ 190 u32 cm3_cache_fun_ctrl; /* 0xA48 */ 191 u32 reserve_0xA4C[108]; /* 0xA4C */ 192 u32 pci_config[3]; /* 0xC00 */ 193 u32 reserve_0xC0C[5]; /* 0xC0C */ 194 u32 pcie_config; /* 0xC20 */ 195 u32 mmio_decode; /* 0xC24 */ 196 u32 reloc_ctrl_decode[2]; /* 0xC28 */ 197 u32 reserve_0xC30[4]; /* 0xC30 */ 198 u32 mailbox_addr; /* 0xC40 */ 199 u32 shared_sram_decode[2]; /* 0xC44 */ 200 u32 bmc_rev_id; /* 0xC4C */ 201 u32 reserve_0xC50[5]; /* 0xC50 */ 202 u32 bmc_device_id; /* 0xC64 */ 203 u32 reserve_0xC68[102]; /* 0xC68 */ 204 u32 vga_scratch[8]; /* 0xE00 */ 205 }; 206 207 #endif /* _ASM_ARCH_SCU_AST2600_H */ 208